Yiu Ming Cheung

Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

In this paper, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC cap, reconstituted carrier material and thickness, and die-attach film, on the warpage after postmold cure and backgrinding of the EMC. The simulation results are compared to the experimental measurements. Also, the thermal performance (junction-to-ambient thermal resistance) of FOWLP with various chip thicknesses is characterized. Finally, some FOWLP important parameters affecting the warpage and thermal performances are recommended.

A high throughput and reliable thermal compression bonding process for advanced interconnections

In this study, a liquid phase contact thermal compression bonding (LPC TCB) process was investigated for fine-pitch copper pillar with solder cap flip chip packages. It offers a high throughput and reliable interconnection with a controllable solder height. A series of LPC TCB experiments using both Chip-on-substrate (CoS) and Chip-on-chip (CoC) packages were performed. The bonding profiles clearly indicate that a high throughput, UPH (units per hour) of 1.2k, could be achieved compared with UPH of ~600 for a conventional TCB-flux process. The results on cross section examination, interfacial microstructure, shear strength and failure mode demonstrated that excellent wetting and robust solder joint could be achieved using LPC TCB process. With a bond head (BH) cooling step, a precise solder height could be obtained based on a pre-determined bonding level, while without a BH cooling step, the solder height remained at a constant value regardless the bonding level. The restoring force from the surface tension was calculated to explain this phenomenon. Finite element analysis (FEA) was also carried out to predict the joint fatigue life for the packages bonded with different solder thickness values.

Stencil printing of underfill for flip chips on organic-panel and Si-wafer assemblies

A high-throughput method of post-assembly underfill is presented in this study. Emphasis is placed on the proposal of a specially designed stencil to print the underfill material for flip chips on large organic-panel and Si-wafer assemblies. After printing, the organic-panel or Si-wafer assemblies are placed on a hot plate for the underfill to totally fill the space between the chips, solder joints and substrates by capillary action, and then cured. The printing time is in a matter of seconds and hundreds or even thousands (depending of chip size and panel- and wafer-substrate size) of assemblies are printed. The cured assemblies are characterized by the C-SAM (C-Mode scanning acoustic microscopy), x-ray, shear test, cross-sectioning, and SEM (scanning electron microscopy). The effects of the viscosity, thermal enhancement, and multiple prints of underfills are examined. It is found that stencil printing of underfill for flip chips on organic-panel and Si-wafer substrates is a very high-throughput, simple, and low cost process.

Investigation into transient characteristics of post-welding shift for opto-electronic pigtail package

We study transient post-welding shift (PWS) with experiment and simulation. Measurement of PWS with non-contact displacement sensor reveals that a typical laser welding of TO-can pigtail package involves transient PWS with multiple characteristic time scales. Finite element modeling (FEM) of a three-dimensional structure with thermo-mechanical coupling helps us visualize the dynamics of the miniscule PWS. This study gives a better understanding on the physical process of transient PWS.

Stencil Printing of Underfill for Flip Chips on Organic-Panel and Si-Wafer Substrates

A high-throughput method of post assembly underfill is presented in this paper. Emphasis is placed on the proposal of a specially designed stencil to print the underfill material for flip chips on large organic-panel and Si-wafer assemblies. After printing, the organic-panel or Si-wafer assemblies are placed on a hot plate for the underfill to totally fill the space between the chips, solder joints, and substrates by capillary action, and then cured. The cured assemblies are characterized by the C-mode scanning acoustic microscopy, X-ray, shear test, cross sectioning, and scanning electron microscopy. The effects of the viscosity, thermal enhancement, and multiple prints of underfills are examined. It is found that stencil printing of underfill for flip chips on organic-panel and Si-wafer substrates is a very high-throughput, simple, and low-cost process.