Nguyen Anh Vu Doan

Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA

Body biasing can be used to control the leakage power and the performance of transistors by changing the threshold voltage after fabrication. Especially, a new process called Silicon-On-Thin BOX (SOTB) CMOS can control the balance of these two factors. When it is applied to a Coarse-Grained Reconfigurable Array (CGRA), the leakage power can be largely reduced by controlling precisely the bias with small domain size. On the other hand, the choices on bias voltages depend on the application executed on the platform, especially its mapping. In this paper, we propose to apply a multi-objective optimization for the application mapping and the body bias control on an energy efficient CGRA called CC-SOTB (Cool Mega Array Cube-SOTB). By using an NSGA-II algorithm for the mapping exploration and Integer Linear Programming (ILP) for the body bias control optimization, we show that it is possible to achieve better power consumption results than in previous works. For instance, in the case of a domain size of 2 rows by 1 column, it is possible to achieve a power reduction ratio up to 43.25%, compared to 21.09% previously, for the studied application. This is however achieved at the cost of a bigger mapping width. Nonetheless, the exploration allows to have finer analyses about both mapping and consumption. Indeed, these promising results show that optimizing the application mapping simultaneously with the body bias control can provide more interesting results, giving deeper quantitative information about trade-off possibilities.

On the use of reference profiles to compute alternative PROMETHEE II rankings: A preliminary study

Engineering decision problems often involve the simultaneous optimization of several conflicting criteria. Among multicriteria decision aid methods, PROMETHEE has gained a lot of attention during the last three decades. Despite its successful application in different fields, some researchers have emphasized that PROMETHEE does not respect the independence to third alternatives assumption. This leads to the so-called “rank reversal” phenomenon (potential manipulation threat); the relative position of two alternatives may depend on a third one. In this paper, inspired by the ideas of reference profiles to establish rankings, we propose a new way to compute an alternative PROMETHEE II ranking that does not suffer from rank reversal (common basis for the pairwise comparisons for all the alternatives). We show on an illustrative example the results given by this new method and observe that the obtained ranking is compatible with the one established with the classical PROMETHEE II method.

MCDA-based methodology for efficient 3D-design space exploration and decision

Recently, the academic and industrial communities have proposed new technologies in order to overcome the physical limitations of the silicon, and among them 3D-Stacked Integrated Circuits (3D-SIC). Manufacturing of 3D-SICs consists in piling up conventional CMOS ICs and creating vertical interconnections between them. This offers new perspectives and levels of performance but the question of efficiently designing them arises since the solution space increases significantly. This paper presents a first approach based on a multi-criteria method in order to be able to efficiently design 3D-SIC. The aim of this work is to quickly explore the design space while considering the numerous criteria involved. This work is a first approach that shows a new design method based on the use of Multi- Criteria Decision Aid (MCDA) tools for efficient 3D-SIC design. The problem considered in this first approach is a global 3D-floorplanning. This work has shown that using MCDA tools can provide objective information that would not be available with the current conventional design methods. Those information provides deep analyses which could answer some of the questions a designer may have about the design space of a circuit. We believe that, with these promising results, this MCDA-based method will allow designers to overcome the growing complexity of designing 3D-SICs.

MCDM Applied to the Partitioning Problem of 3D-Stacked Integrated Circuits

In the past decades, the microelectronic industry has been following the Moore’s law to improve the performance of integrated circuits (IC). However, it will probably be impossible to follow this law in the future due to physical limitations appearing with the miniaturization of the transistors below a certain threshold without innovation. In order to overcome this problem, new technologies have emerged, and among them the 3D-Stacked Integrated Circuits (3D-SIC) have been proposed. 3D-SICs can bring numerous advantages in the design of future ICs but at the cost of additional design complexity due to their highly combinatorial nature, and the optimization of several conflicting criteria. Currently, most decisions about the production of a circuit are based on subjective considerations. In order to help designers facing choices when developing 3D chips, we present in this study an application of multi-criteria decision making (MCDM) tools, and more precisely the PROMETHEE methods, to the partitioning problem of 3D-SICs. Our work addresses two different production scenarios for the design of an OpenSPARC-T2 System-on-Chip. With this study, one can observe that multi-criteria analyzes can give to designers insights into the trade-off possibilities for the optimization of a circuit. In addition, the PROMETHEE methodology can help a designer facing choices and provide a transparent process when selecting a valid chip to develop. This shows that applying MCDM tools such as PROMETHEE to design 3D-SICs can indeed help designers to make a better use of this technology.

On the use of Multi-Criteria Decision Aid tools for the efficient design of 3D-Stacked Integrated Circuits: A preliminary study

In past decades, the electronic industry has been following the Moores law to improve the performance of CMOS integrated circuits (IC). However, it will probably be impossible to follow this law in the future due to physical limitations appearing with the miniaturization of the transistors below a certain threshold. In order to overcome this problem, new technologies have emerged, and among them the 3D-Stacked Integrated Circuits (3D-SIC) have been proposed to keep the Moores momentum alive. 3D-SICs can bring numerous advantages in the design of future ICs but at the cost of additional design complexity due to their highly combinatorial nature, and requiring the optimization of several conflicting criteria. In this paper, we present a preliminary study of tools that can help the design of 3D-SICs, using multi-criteria analysis. Our study has targeted one of the main issues in the design of 3D-SICs: the floorplanning. This work has shown that the use of Multi-Criteria Decision Aid (MCDA) tools can provide relevant and objective analysis of the problem that may not be feasible with the current design methods. We believe that these promising results will allow designers to overcome the complexity of designing 3D-SICs.