Dragomir Milojevic

Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip

To ensure low power consumption while maintaining flexibility and performance, future systems-on-chip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, networks-on-chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and destination. State-of-the-art NoCs currently exploit time-division multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit set-up time. We propose an alternative solution based on spatial division multiplexing (SDM). This paper describes our design of an SDM-based network, discusses design alternatives for network implementation and shows why SDM can be better adapted to NoCs than TDM in a specific context. Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. A comparison is also performed with a state-of-the-art industrial reference NoC: Arteris.

Power-Aware Real-Time Scheduling upon Dual CPU Type Multiprocessor Platforms

Nowadays, most of the energy-aware real-time scheduling algorithms belong to the DVFS (Dynamic Voltage and Frequency Scaling) framework. These DVFS algorithms are usually efficient but, in addition to often consider unrealistic assumptions: they do not take into account the current evolution of the processor energy consumption profiles. In this paper, we propose an alternative to the DVFS framework which preserves energy, while considering the emerging technologies. We introduce a dual CPU type multiprocessor platform model (compatible with any general-purpose processor) and a non-DVFS associated methodology which considerably simplifies the energy-aware real-time scheduling problem, while providing significant energy savings.

An integrated robotic system for antipersonnel mines detection

Abstract In this paper robotic systems for antipersonnel mines detection are presented. Robots with different locomotion principles have been developed to carry mines detection sensors. In this project, many different aspects including mechanics, control and positioning have been addressed. After a short review of the project and a description of the system components, the control and communication architecture of the robotic detection systems is presented. One of the most important issues in this application was the synchronisation of the processes between the microcontrollers and remote computers. The method that has been implemented has proven to be robust and the different systems have been used to acquire very useful data for the research community.

Thermal characterization of cloud workloads on a power-efficient server-on-chip

We propose a power-efficient many-core server-on-chip system with 3D-stacked Wide I/O DRAM targeting cloud workloads in datacenters. The integration of 3D-stacked Wide I/O DRAM on top of a logic die increases available memory bandwidth by using dense and fast Through-Silicon Vias (TSVs) instead of off-chip IOs, enabling faster data transfers at much lower energy per bit. We demonstrate a methodology that includes full-system microarchitectural modeling and rapid virtual physical prototyping with emphasis on the thermal analysis. Our findings show that while executing CPU-centric benchmarks (e.g. SPECInt and Dhrystone), the temperature in the server-on-chip (logic+DRAM) is in the range of 175-200°C at a power consumption of less than 20W, exceeding the reliable operating bounds without any cooling solutions, even with embedded cores. However, with real cloud workloads, the power density in the server-on-chip remains much below the temperatures reached by the CPU-centric workloads as a result of much lower power burnt by memory-intensive cloud workloads. We show that such a server-on-chip system is feasible with a low-cost passive heat sink eliminating the need for a high-cost active heat sink with an attached fan, creating an opportunity for overall cost and energy savings in datacenters.

DRAM-on-logic Stack – Calibrated thermal and mechanical models integrated into PathFinding flow

In this paper, we present thermal and mechanical characterization of a DRAM-on-logic stack. Our experimental data indicates that a holistic optimization of design and technology is needed to achieve working 3D stacks. Particularly, the stack organization and TSV/μbump layout must be fine-tuned together with the 3D technology for managing mechanical and thermal challenges. In order to support system designers, we propose hereto a dedicated thermal and mechanical model, integrated into the design flow. We also indicate the data required from foundries and OSATs to achieve good fidelity with measurement results.

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study

New technologies for manufacturing 3D Stacked ICs offer numerous opportunities for the design of complex and effcient embedded systems. But these technologies also introduce many design options at system/chip design level, hard to grasp during the complete design cycle. Because of the sequential nature of current design practices, designers are often forced to introduce design margins to meet required specications, resulting in sub-optimal designs. In this paper we introduce new design methodology and practical tool chain, called PathFinding Flow, that can help designers to easily trade-off between different system level design choices, physical design and/or technology options and understand their impact on typical design parameters such as cost, performance and power. Proposed methodology and the tool chain will be demonstrated on a practical case study, involving fairly complex Multi-Processor System-on-Chip using Network-on-Chip for communication medium. With this example we will show how High-Level Synthesis can be used to quickly move from high-level to RTL models, necessary for accurate physical prototyping for both computation and communication. We will also show how the possibility of design iteration, through the mechanism of feedback based on physical information from physical prototyping, can improve design performance. Finally, we will show how we can move in no time from traditional 2D to 3D design and how we can measure benets of such design choice.

An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations

We present a compact model that provides a quick estimation of the stress and mobility patterns around arbitrary configurations of Through-Silicon Vias (TSVs). No separate TCAD simulations are required for these configurations. It estimates nFET and pFET mobility for industry-standard as well as for (100)/<100> substrate orientations. As the model provides mobility info in less than 0.1 millisecond/transistor/TSV, it is possible to be used in combination with layouting tools and circuit simulators to optimise layouts of circuits for digital and analog applications. The model has been integrated into the 3D PathFinding flow, for steering 3D IO placement during stack definition.

Power dissipation of the network-on-chip in a system-on-chip for MPEG-4 video encoding

In this paper we present a multi-processor system-on-chip (MPSoC) platform with six computational and four memory nodes interconnected with Arteris network-on-chip (NoC). The platform is dedicated for real-time video encoding applications for high resolution images (HDTV) and frame rates of up to 30 fps. Extensive experiments established the power dissipation models of all individual NoC components, i.e. network interfaces, routers and wires. Based on these power models and the NoC topology we built the power model of the complete NoC. Finally we derive the power dissipation of the NoC for MPEG4 simple profile encoder. The results show that depending on the image resolution the power dissipation of the communication infrastructure vary between 15 and 22 mW, which is comparable with the state of the art dedicated low-power implementations.

Design issues in heterogeneous 3D/2.5D integration

Efficient processing of fine-pitched Through Silicon Vias, micro-bumps and back-side re-distribution layers enable face-to-back or face-to-face integration of heterogeneous ICs using 3D stacking and/or Silicon Interposers. While these technology features are extremely compelling, they considerably stress the existing design practices and EDA tool flows typically conceived for 2D systems. With all system, technology and implementation level options brought with these features, the design space increases to an extent where traditional 2D tools cannot be used any more for efficient exploration. Therefore, the cost-effective design of future 3D ICs products will require new planning and co-optimisation techniques and tools that are fast and accurate enough to cope with these challenges. In this paper we present design methodology and the practical EDA tool chain that covers different aspects of the design flow and is specific to efficient design of 3D-ICs. Flow features include: fast synthesis and 3D design partitioning at gate level, TSV/micro-bump array planning, 3D floor planning, placement and routing, congestion analysis, fast thermal and mechanical modeling, easy technology vs. implementation trade-off analysis, 3D device models generations and Design-for-Test (DfT). The application of the tool chain is illustrated using concrete example of a real-world design, showing not only the applicability of the tool chain, but also the benefits of heterogeneous 2.5 and 3D integration technologies.

Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management

In this paper we describe a general purpose, homogeneous Multi-Processor System-on-Chip (MPSoC) based on 9 processing clusters using COFFEE RISC processors and a hierarchical Network-on-Chip implemented on an FPGA device. The MPSoC platform integrates a cluster clock gating technique, enabling independent core and memory sleep modes. Low cluster turn-on delay allows frequent use of such technique, resulting in power savings. In order to quantify the performance of the proposed platform and the reduction of power consumption, we implement Target Cell Search part of the WCDMA, a well known SDR application. We show that the proposed MPSoC platform achieves an important speed-up (7.3X ) when compared to comparable single processor platform. We also show that a significant reduction in dynamic power consumption can be achieved (50% for the complete application) using the proposed cluster clock-gating technique.