Frédéric Robert

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs

To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, Networks-on-Chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and destination. State-of-the-art NoCs currently exploit Time-Division Multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit set-up time.We propose an alternative solution based on Spatial Division Multiplexing (SDM). This paper describes our first design of an SDM-based network, discusses design alternatives for network implementation and shows why SDM should be better adapted to NoCs than TDM for a limited number of circuits.Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. SDM thus deserves to be explored in more depth, and in particular in combination with TDM in a hybrid scheme.

Design style case study for embedded multi media compute nodes

Users expect future handheld devices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on both (realtime) performance and energy consumption and forces designers to optimise all parts of their platform. In this experiment we focus on the different processor core design options for embedded platforms, including the effect of instruction memory hierarchy on the energy consumption. The results show that significant improvements for energy efficiency and/or performance over currently used RISC or VLIW processors can be achieved. We conclude, based on concrete data for a realistic application, that different styles, including both configurable hardware and instruction set processors, find their way into heterogeneous platforms and designers need to be aware of the trade-offs. Secondly, we show for the same application task that a heavily optimised instruction/configuration memory hierarchy can significantly reduce the energy consumption of this part, so it forms a crucial part of every energy aware design.

A framework introducing model reversibility in SoC design space exploration

In this paper we present a general framework for the support of flexible models representation and execution in the context of SoC design space exploration. Coming as a C++ library, it allows the user to gather models from its own and existing models into larger and more complete models. Compared to existing modeling systems we introduce the notion of model reversibility that allows the user to turn any parameter appearing in a model into the output : it increases the model flexibility and enables its reuse in very different problems. Aside from providing specification and execution support, the framework also permits dynamic model sensitivity analysis and efficient parameter sensitivity analysis for closed-formed models. Through this paper we explain our original 3-level hierarchical representation of model and explain meanwhile how it offers flexibility and model robustness using a XML schema grammar.

A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation

In this paper we present a flexible performance estimation tool called Nessie developed to provide system-on-chip designers with automated multi-objective design space exploration and its related tool called Yeti building and executing reusable closed-formed models. After reviewing the existing closed-formed expressions based and application/platform mapping performance estimation tools, we propose an hybrid tool to cope with their limitations. We present a brief summary of the functionalities of Yeti and describe Nessie, our hierarchical application/platform performance estimation mapping tool which banalizes all the degrees of freedom for in-depth design space exploration and introduces multi-objective modeling. Through this paper, we explain how the combination of these tools provides the designer with innovative and powerful functionalities for performance prediction at the earlier stages of the design flow.

Impact of device and interconnect process variability on clock distribution

For sub-28nm, process variations became more important. Clock distribution networks are sensitive to those variations because they lead to increased clock skew, which translates to a deterioration of the performance. In this scope, it is the first time that different existing processes are compared. We consider self-aligned double patterning (SADP) and triple expose triple etch (LELELE). First we study the sensitivity of clock skew to interconnect capacitance and resistance. Next we present the influence of the geometry of the tree as the chip size and the clock tree depth. We also investigate the performance of adding air gaps between wires. The results show that the skew is more sensitive to the variation of resistance of the lower metal layers (Mx) and of capacitance of the upper metal layers (Mz). Thus we choose triple-expose triple-etching (LELELE) process for Mx and a relaxed metal pitch for Mz in order to optimize RC-variations. By increasing the depth of the tree the front-end of line (FEOL) influence on skew becomes more dominant with respect to the back-end of line (BEOL) as the number of drivers grows up exponentially with respect to the depth. In the end, we find a trade-off between power consumption and skew deviation with the introduction of air gaps between wires. For a reduction of 9% of the capacitance thanks to the air gaps, the power consumption decreases by the same percentage (6%) as the skew deviation.

Study of hardware implementations of fast tracking algorithms

Real-time track reconstruction at high event rates is a major challenge for future experiments in high energy physics. To perform pattern-recognition and track fitting, artificial retina or Hough transformation methods have been introduced in the field which have to be implemented in FPGA firmware. In this note we report on a case study of a possible FPGA hardware implementation approach of the retina algorithm based on a Floating-Point core. Detailed measurements with this algorithm are investigated. Retina performance and capabilities of the FPGA are discussed along with perspectives for further optimization and applications.