Nicholas C. M. Fuller

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I<inf>DSAT</inf> = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V<inf>DD</inf> = 1 V and off-current I<inf>OFF</inf> = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed for continuous FinFET SRAM cell-size scaling.

Effect of plasma interactions with low- κ films as a function of porosity, plasma chemistry, and temperature

Integration of new low-κ interlayer dielectrics (ILD) with current damascene schemes is a continuing issue in the microelectronics industry. During integration of the ILD, processing steps such as plasma etching, resist strip, and chemical-mechanical planarization are known to chemically alter a layer of the dielectric. Here, porous organosilicate glass (OSG) ILD films, which—according to the 2004 edition of the International Technology Roadmap for Semiconductors—are projected for use in the 65 and 45 nm nodes, are investigated. spectroscopic ellipsometry, x-ray photoelectron spectroscopy, and Fourier transform infrared spectroscopy are used to characterize the modified layer of the ILD after exposure to O2 or H2 resist strip plasmas. The effects of the two types of plasma etch chemistries on the formation of the modified layer were found to differ significantly. These effects include both the degree of modification (i.e., chemical composition) and depth of the modified layer. A key difference between the...

MRONLINE: MapReduce online performance tuning

MapReduce job parameter tuning is a daunting and time consuming task. The parameter configuration space is huge; there are more than 70 parameters that impact job performance. It is also difficult for users to determine suitable values for the parameters without first having a good understanding of the MapReduce application characteristics. Thus, it is a challenge to systematically explore the parameter space and select a near-optimal configuration. Extant offline tuning approaches are slow and inefficient as they entail multiple test runs and significant human effort. To this end, we propose an online performance tuning system, MRONLINE, that monitors a jobs execution, tunes associated performance-tuning parameters based on collected statistics, and provides fine-grained control over parameter configuration. MRONLINE allows each task to have a different configuration, instead of having to use the same configuration for all tasks. Moreover, we design a gray-box based smart hill climbing algorithm that can efficiently converge to a near-optimal configuration with high probability. To improve the search quality and increase convergence speed, we also incorporate a set of MapReduce-specific tuning rules in MRONLINE. Our results using a real implementation on a representative 19-node cluster show that dynamic performance tuning can effectively improve MapReduce application performance by up to 30% compared to the default configuration used in YARN.

FinFET performance advantage at 22nm: An AC perspective

At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.

Effect of radical species density and ion bombardment during ashing of extreme ultralow-κ interlevel dielectric materials

The significance of ion impact and radical species density on ash-induced modification of an extreme ultralow-κ interlevel dielectric (ILD) material (κ<2.0) in a patterned single damascene structure exposed to Ar∕O2 and Ar∕N2 dual frequency capacitive discharges is determined by combining plasma diagnostics, modeling of the ion angular distribution function, and material characterization such as angle resolved x-ray photoelectron spectroscopy. Radical species density was determined by optical emission actinometry under the same conditions and in the same reactor in a previous study by the present authors. ILD modification is observed and correlated with changes in the plasma for a range of pressures (5–60mTorr), bias powers (0–350W), and percent Ar in the source gas (0%, 85%). For the Ar∕O2 discharge, extensive modification of the ILD sidewall was observed for significant ion scattering conditions, whereas minimal modification of the ILD sidewall was observed under conditions of minimal or no ion scatteri...

Characterization of neutral species densities in dual frequency capacitively coupled photoresist ash plasmas by optical emission actinometry

Reactive neutral species densities for various conditions in dual frequency capacitively coupled discharges of Ar∕O2, Ar∕N2, and Ar∕H2 were determined using optical emission spectroscopy, Kr actinometry, and modeling. The reactive neutral species probed in this work include O, O2, N, N2, H, and H2. Densities are reported as a function of pressure (5–60mTorr), percent Ar in the feed gas (1%–86%), source power (50–800W), and bias power (0W, 200W). It was found that increasing the pressure from 5to60mTorr resulted in order of magnitude increases in atomic species densities for all ash chemistries. At 30mTorr, percent dissociation is relatively low (⩽15%) for all species. Also, at 30mTorr, the addition of Ar resulted in a small decrease in N and H densities, but an order of magnitude increase in O density. Based on modeling, it is proposed that the increase in O density is due to an increasing contribution of Penning dissociation with increasing Ar density. Only the source power contributed significantly to O...

Sub-30 nm pitch line-space patterning of semiconductor and dielectric materials using directed self-assembly

The authors demonstrate pattern transfer of 29-nm-pitch self-assembled line-space polystyrene-poly(methyl methacrylate) patterns generated by graphoepitaxy into three important materials for semiconductor device integration: silicon, silicon nitride, and silicon oxide. High fidelity plasma etch transfer with production-style reactors was achieved through co-optimization of multilayer masking film stacks and reactor conditions. The authors present a systematic study of the line edge roughness (LER) and line width roughness evolution during pattern transfer. Application of a postetch annealing process shows reduction of the LER of silicon features from around ∼3 nm to less than 1.5 nm. These results further demonstrate that directed self-assembly-based patterning may be a suitable technique for semiconductor device manufacturing.

Gate-all-around silicon nanowire MOSFETs and circuits

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET IDSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage VDD = 1 V and off-current IOFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed. Additionally, we observe a divergence of the nanowire capacitance from the planar limit, as expected, as well as enhanced device self-heating for smaller diameter nanowires. We have also applied this method to making functional 25-stage ring oscillator circuits.

VMAR: Optimizing I/O Performance and Resource Utilization in the Cloud

A key enabler for standardized cloud services is the encapsulation of software and data into VM images. With the rapid evolution of the cloud ecosystem, the number of VM images is growing at high speed. These images, each containing gigabytes or tens of gigabytes of data, create heavy disk and network I/O workloads in cloud data centers. Because these images contain identical or similar OS, middleware, and applications, there are plenty of data blocks with duplicate content among the VM images. However, current deduplication techniques cannot efficiently capitalize on this content similarity due to their warmup delay, resource overhead and algorithmic complexity.