Isaac Lauer

Low power circuit design based on heterojunction tunneling transistors (HETTs)

The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low supply voltages. This paper investigates extremely-low power circuits based on new Si/SiGe HEterojunction Tunneling Transistors (HETTs) that have subthreshold swing < 60 mV/decade. Device characteristics as determined through Technology Computer Aided Design (TCAD) tools are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that a HETT-based ring oscillator (RO) shows a 9--19X reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional MOSFETs, namely asymmetric current flow and increased Miller capacitance, analyzing their effect on circuit behavior and proposing methods to address them. Finally, HETT characteristics have the most dramatic impact on SRAM operation and hence we propose a novel 7-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7-37X reduction in leakage power compared to CMOS.

Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can be integrated to density targets commensurate with CMOS scaling needs of the 10 nm node and beyond. In addition, this work achieves the highest performance for GAA SiNW NFETs at a gate pitch below 100 nm.

Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)

The theoretical lower limit of subthreshold swing in mosfets (60 mV/decade) significantly restricts low-voltage operation since it results in a low ON -to- OFF current ratio at low supply voltages. This paper investigates extremely low-power circuits based on new Si/SiGe heterojunction tunneling transistors (HETTs) that have a subthreshold swing of . Device characteristics, as determined through technology computer aided design tools, are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that an HETT-based ring oscillator (RO) shows a 9-19 times reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional mosfets, namely, asymmetric current flow and increased Miller capacitance, analyze their effect on circuit behavior, and propose methods to address them. HETT characteristics have the most dramatic impact on static random access memory (SRAM) operation and we propose a novel seven-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7-37 times reduction in leakage power compared to CMOS.

Channel doping impact on FinFETs for 22nm and beyond

The natural choice to achieve multiple threshold voltages (Vth) in fully-depleted devices is by choosing the appropriate gate workfunction for each device. However, this comes at the cost of significantly higher process complexity. The absence of a body contact in FinFETs and insensitivity to back-gate bias leaves the conventional channel doping approach as the most practical technique to achieve multiple Vth. This choice, however, introduces a variable that is usually not considered in the context of fully depleted devices. For the first time, we demonstrate a multiple Vth solution at relevant device geometries and gate pitch for the 22nm node. We investigated the impact of FinFET channel doping on relevant device parameters such as Tinv, mobility, electrostatic control and Vth mismatch. We also show that Vth extraction by the “constant current” method could mislead the DIBL analysis of devices with greatly different channel mobility.

Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance

We demonstrate a process flow for creating gate-all-around (GAA) Si nanowire (SiNW) MOSFETs with minimal deviation from conventional replacement metal gate (RMG) finFET technology as used in high-volume manufacturing. Using this technique, we demonstrate the highest DC performance shown for GAA SiNW MOSFETs at sub-100 nm gate pitch, and functional high-speed ring oscillators.

Effect of Uniaxial Strain on the Drain Current of a Heterojunction Tunneling Field-Effect Transistor

The electrical characteristics of a heterojunction tunneling field-effect transistor (HETT), with a p-type Si0.75Ge0.25 source, have been measured as a function of strain. HETTs with channel transport and applied strain both in the [110] direction show a smooth monotonic change in drain current over a range of 0.09% compressive to 0.13% tensile strain. A measure γ = (d/d ln JD)(d ln JD/ds) |s=0 of the effect of strain s on tunneling current JD is proposed, which captures the dependence of the tunneling exponential argument on strain. An experimental value of γ = -11.7 is extracted for the tensile case and compared to simulation results. We found theoretically that the value and sign of depend sensitively on the built-in strain at the Si-SiGe interface.

Operational amplifier based test structure for transistor threshold voltage variation

A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation. The test structure also includes an on-chip clock generator and address decoders to scan through the arrays. It can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing. Hardware results in a 65 nm technology are presented.

Are Si/SiGe Tunneling Field-Effect Transistors a Good Idea?

Introduction. The ability to scale CMOS to future technology nodes is jeopardized primarily by power constraints. Supply voltage scaling is the best method to reduce power consumption in logic circuits; however, the thermionic nature of the turn-off mechanism in MOSFETs forces a fundamental trade-off between leakage power and performance when the voltage is reduced. Tunneling field effect transistors (TFETs) could overcome this limitation since these devices have been theoretically shown to be capable of subthreshold slopes < 60 mV/decade [1]. However, the band gap of silicon (1.12 eV) is too large to provide acceptable drive currents in Si-based TFETs. TFETs fabricated using Si/SiGe heterojunctions [2] have the potential for increased drive current since the type-II band alignment reduces the effective band gap for tunneling at the source electrode. In this talk, I will show experimental results on Si/SiGe heterojunction tunneling transistors (HETTs), along with quantum transport simulations on a variety of heterojunction TFET geometries, and then describe the implications of these results on the viability of the Si/SiGe material system for TFET fabrication. Si/SiGe HETTs. The devices were fabricated using a conventional CMOS process flow that was modified to allow the source and drain electrodes to be formed in separate processing steps. The devices utilized SOI starting substrates and a high-κ/poly gate stack. The n drain was formed by conventional As implantation and anneal, while the source electrode was formed by selective etching of Si underneath the gate electrode and regrowth of in-situ-doped p Si1-xGex. Typical Id vs. Vgs characteristics at room temperature for HETTs with source Ge concentrations of 7% and 25% are shown in Fig. 2 [3]. The improved performance for the devices with x = 25% over x = 7% provides a clear indication of the heterojunction benefit on TFET performance. However, the devices fall short of achieving sub-60 mV/dec subthreshold slopes or the necessary drive currents for practical applications. Broken-gap TFETs. In order to further explore the heterojunction band structure requirements for TFETs, quantum transport simulations are performance on a variety of HETTs with band alignment ranging from staggered to broken gap [4]. The results, shown in Fig.3, indicate that the optimal performance is achieved in broken-gap heterojunction devices. These results further demonstrate the efficacy of the heterojunction design in improving TFET drive current, but also suggest that novel device geometries [5] or material systems with direct band gaps (e.g. III-Vs [6], graphene nanoribbons [7]) may be needed to achieve the performance levels necessary for practical applications. References. [1] J. Appenzeller, et al., Phys. Rev. Lett., 2004, [2] O. Nayfeh, et al., IEEE Elect. Dev. Lett., 2008, [3] S. J. Koester, et al., unpublished, [4] S. Koswatta, et al., IEDM, 2009, [5] A. Bowander, et al., VLSI., 2008, [6] S. Mookerjea, et al., IEDM, 2009, [7] Q. Zhang, et al., IEEE Elect Dev. Lett., 2008. n+ poly

Operational Amplifier Based Test Structure for Quantifying Transistor Threshold Voltage Variation

A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation. The test structure also includes an on-chip clock generator and address decoders to scan through the arrays. It can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing. Hardware results in a 65-nm technology are presented. The significance of the bias dependence of Vt variation is discussed for SRAM product designs.

On implementation of embedded phosphorus-doped SiC stressors in SOI nMOSFETs

We report a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. We identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (Csub) of ~1.0%, high performance nFETs with SiC stressors demonstrate ~9% enhanced Ieff and ~15% improved Idlin against the well calibrated control devices. It is found that the tensile liner technique provides further performance improvement for nFETs with SiC stressors, whereas the stress memory technique (SMT) does not provide performance gain in a laser annealing process that is used to preserve SiC strain. The material quality of the SiC stressors strongly affects strain transfer.