Nicolas Breil

Low Temperature Implementation of Dopant-Segregated Band-edge Metallic S/D junctions in Thin-Body SOI p-MOSFETs

This paper proposes the implementation of a dopant segregated band-edge silicide using implantation-to-silicide and low temperature activation (500degC). The integration of platinum silicide coupled to boron segregation demonstrates a 50% enhancement of the current drive over the dopant-free approach. RF characterization unveils a cut-off frequency fT of 180 GHz at Lg=30 nm without application of channel stressors.

RF Small-Signal Analysis of Schottky-Barrier p-MOSFET

This paper presents a detailed RF study for source/drain Schottky-barrier (SB) MOSFETs. Using on-wafer -parameters, high-frequency (HF) figures-of-merit (FoMs) and small-signal equivalent circuits (SSEC) are first extracted and discussed for a -gate-length SB MOSFET. Then, using ac simulations, HF FoMs sensitivity along SB height and underlap length variations are subsequently presented. The whole study provides, for SB MOSFETs, a deep understanding of key ac-element (transconductances and capacitances) behavior as well as process-parameter optimization to achieve the best HF FoMs.

Optimization of RF Performance of Metallic Source/Drain SOI MOSFETs Using Dopant Segregation at the Schottky Interface

This letter presents a detailed investigation of the impact of dopant segregation (DS) on radio-frequency (RF) performance of p-type 110-nm undoped ultrathin-body Schottky-barrier (SB) silicon-on-insulator MOSFETs. It is shown that optimizing this dopant-segregated layer via careful control of the dopant concentration (N SEG) and lateral extension (L SEG) reduces the apparent potential barrier height at the Schottky junctions. This results in highly reduced source/drain (S/D) contact resistances, along with a peak fT value obtained at very low dc power consumption (45 muW/mum at VDS = -2 V), which is very promising to address low-power low-voltage analog applications. Finally, the source resistance extracted from this RF study ( ~120 Omegamiddotmum) clearly demonstrates the ability of the DS SB S/D architecture to pursue the silicon roadmap beyond the 22-nm node.

Recent advances in metallic source/drain MOSFETs

This paper reports on advances in metallic source/drain MOSFETs covering material engineering, integration issues such as metal/silicide selective etching and electrical performance in both DC and RF regimes. A soft and scalable etching procedure that selectively eliminates metallic platinum (Pt) without altering the platinum silicide phase (PtSi) is proposed. Strategies of Schottky barrier reduction based on low temperature dopant segregation are exemplified when PtSi is coupled to boron and arsenic. Finally, the integration of p-type boron-segregated contacts in thin-film SOI p-MOSFETs reveals state-of-the-art results both for DC and RF operation.

UHV fabrication of the ytterbium silicide as potential low Schottky barrier S/D contact material for n-type MOSFET

Ytterbium silicide provides a low Schottky barrier height to electron on n-type silicon. This property makes this material very attractive for the realization of Source/Drain contacts for n-type MOSFETs. In this communication, the study of structural and electrical properties of YbSi2-x fabricated at different temperature in Ultra-High Vacuum condition without any protective layers is presented. N-type SB-MOSFETs with ytterbium silicide based S/D contacts were fabricated at optimal silicidation temperatures on SOI substrate with an ultra thin body.

Issues Associated to Rare Earth Silicide Integration in Ultra Thin FD SOI Schottky Barrier nMOSFETs

The paper focuses on specific issues associated to rare earth silicide integration on UTB-SOI substrate with a particular attention to erbium and ytterbium silicides. Due to the limited Si source, defects generation on SOI is prevented compared to bulk substrate. Reaction of RE with dielectric materials limits the temperature of silicidation. It is shown that RE S/D MOSFETs are still limited in current-drive by the Schottky barrier height.

Investigation of High Frequency Performance for Schottky-Barrier p-MOSFET

Schottky-barrier source/drain (S/D) MOSFETs (SB-MOS) have recently demonstrated leading edge high frequency (HF) performance, featuring a 280 GHz current gain cut-off frequency fT at 30 nm of gate length. Although this figure represents the best ever recorded fT for a p-MOSFET, little effort has been produced, so far, to analyze key small signal elements (SSE) such as the transconductance G m and the total input capacitance Cgg that directly impact fT. This work demonstrates that the loss of transconductance related to the Schottky barrier (SB) is counterbalanced by a reduction of the total gate capacitance

TEM studies of PtSi low Schottky-barrier contacts for source/drain in MOS transistors

Transmission electron microscopy methods were used to determine the impact of two different implantation processes on the morphology of platinum silicide layers constituting low Schottky barrier contacts intended as the source/drain in MOS transistors. These processes are very promising candidates for the reduction of the Schottky barrier height (SBH) of contacts and are realized by (i) implantation-through-metal (ITM) followed by dopant-segregation induced by silicidation annealing and (ii) implantation-through-silicide (ITS) followed by dopant-segregation due to the post-silicidation annealing. The studies showed that depending on the type and conditions of the process (ITM or ITS with various post-silicidation annealing temperatures) different morphologies of PtSi layers and PtSi/Si interfaces roughnesses are observed. Better quality silicide layers and silicide/silicon interfaces were found for samples after the ITS process with post-silicidation annealing at 500°C than for samples after the ITM process or the ITS process with post-silicidation annealing at temperatures not exceeding 400°C.The observed microstructure of grains and interfaces in these samples, along with the impact of the dopant-segregation, may significantly influence the SBH value. The diffraction patterns and EDXS measurements revealed that regardless of the process type, the formed silicide layer is always PtSi.