Raphael Valentin

Low Temperature Implementation of Dopant-Segregated Band-edge Metallic S/D junctions in Thin-Body SOI p-MOSFETs

This paper proposes the implementation of a dopant segregated band-edge silicide using implantation-to-silicide and low temperature activation (500degC). The integration of platinum silicide coupled to boron segregation demonstrates a 50% enhancement of the current drive over the dopant-free approach. RF characterization unveils a cut-off frequency fT of 180 GHz at Lg=30 nm without application of channel stressors.

RF Small-Signal Analysis of Schottky-Barrier p-MOSFET

This paper presents a detailed RF study for source/drain Schottky-barrier (SB) MOSFETs. Using on-wafer -parameters, high-frequency (HF) figures-of-merit (FoMs) and small-signal equivalent circuits (SSEC) are first extracted and discussed for a -gate-length SB MOSFET. Then, using ac simulations, HF FoMs sensitivity along SB height and underlap length variations are subsequently presented. The whole study provides, for SB MOSFETs, a deep understanding of key ac-element (transconductances and capacitances) behavior as well as process-parameter optimization to achieve the best HF FoMs.

Optimization of RF Performance of Metallic Source/Drain SOI MOSFETs Using Dopant Segregation at the Schottky Interface

This letter presents a detailed investigation of the impact of dopant segregation (DS) on radio-frequency (RF) performance of p-type 110-nm undoped ultrathin-body Schottky-barrier (SB) silicon-on-insulator MOSFETs. It is shown that optimizing this dopant-segregated layer via careful control of the dopant concentration (N SEG) and lateral extension (L SEG) reduces the apparent potential barrier height at the Schottky junctions. This results in highly reduced source/drain (S/D) contact resistances, along with a peak fT value obtained at very low dc power consumption (45 muW/mum at VDS = -2 V), which is very promising to address low-power low-voltage analog applications. Finally, the source resistance extracted from this RF study ( ~120 Omegamiddotmum) clearly demonstrates the ability of the DS SB S/D architecture to pursue the silicon roadmap beyond the 22-nm node.

High-Frequency and Noise Performances of 65-nm MOSFET at Liquid Nitrogen Temperature

In this paper, the high-frequency properties of MOSFETs at low-temperature operation are investigated through measurements and electrical simulations. The experimental results show that the device achieves a 335-GHz fmax and a 300-GHz ft when operating at low temperature (78 K), which constitutes, respectively, a 78% and 34% improvement compared to the room temperature performances (296 K). The minimum noise figure NFmin decreases from 1.4 dB (296 K) to 0.5 dB at 30 GHz (78 K), while the associated gain increases from 8 to 12 dB

MOSFETs RF Noise Optimization via Channel Engineering

In this letter, we propose a design methodology to enhance the High Frequency noise performance of the traditional CMOS technology via channel engineering. We show that the intrinsic noise correlation coefficient (C) of the conventional CMOS (~0.4 or lower) limits the noise performance. By lateral nonuniformly doping the channel, this value of C can be enhanced to as high as ~0.9 in the weak inversion regime and this in turn improves the NFmin of the device. Key noise parameters are carefully compared and analyzed in detail with the state-of-the-art GaAs-based pHEMT and nanoscaled CMOS technology. This letter offers another viable option for achieving CMOS with low power, low voltage, and with much improved noise performance without the need to scale the device.

Recent advances in metallic source/drain MOSFETs

This paper reports on advances in metallic source/drain MOSFETs covering material engineering, integration issues such as metal/silicide selective etching and electrical performance in both DC and RF regimes. A soft and scalable etching procedure that selectively eliminates metallic platinum (Pt) without altering the platinum silicide phase (PtSi) is proposed. Strategies of Schottky barrier reduction based on low temperature dopant segregation are exemplified when PtSi is coupled to boron and arsenic. Finally, the integration of p-type boron-segregated contacts in thin-film SOI p-MOSFETs reveals state-of-the-art results both for DC and RF operation.

Investigation of High Frequency Performance for Schottky-Barrier p-MOSFET

Schottky-barrier source/drain (S/D) MOSFETs (SB-MOS) have recently demonstrated leading edge high frequency (HF) performance, featuring a 280 GHz current gain cut-off frequency fT at 30 nm of gate length. Although this figure represents the best ever recorded fT for a p-MOSFET, little effort has been produced, so far, to analyze key small signal elements (SSE) such as the transconductance G m and the total input capacitance Cgg that directly impact fT. This work demonstrates that the loss of transconductance related to the Schottky barrier (SB) is counterbalanced by a reduction of the total gate capacitance

Influence of gate offset spacer width on SOI MOSFETs HF properties

This work focuses on the influence of the gate spacer offset width (L_offset) on SOI MOSFET high frequency (HF) properties. For this purpose, the DC simulated results were calibrated on experimental data of a 130 nm SOI partially depleted technology. Variations of L_offset were subsequently applied to study its impact on different HF figures of merit (f_t, f_max)

Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET

In this paper, we present the investigation of narrow-width effects (NWEs) on partially depleted (PD) silicon-on-insulator (SOI) with different gate shape topologies. Based on dc/ac measurements and TCAD simulations, it shows detailed clarifications of body-tied-induced NWEs. The overall study demonstrates relationship between gate shape topologies, body-tied shape, and electrical width of the transistor. Provided physical-based analytical models are able to capture peak GM and CGG as function of gate length, transistor width, physical gate-overlap width, and number of body tied. This results in improving the overall model accuracy of body contact and floating-body PD SOI MOSFETs.