Nicolo Morgana

Grayscale lithography: 3D structuring and thickness control

Grayscale lithography has become a common technique for three dimensional structuring of substrates. In order to make the process useful for manufacturing of semiconductor and in particular optoelectronic devices, high reproducible and uniform final film thicknesses are required. Simulations based on a calibrated resist model are used to predict customized process parameters from pixel layout to 3d substrate patterning. Multiple, arbitrary resist heights are reached by using i-line lithography. Scalable and uniform transfer of discrete step heights into oxide are realized by multiple alternating high selective resist and oxide (MASO) etch. Requirements and limitations of reliable 3D film thickness and uniformity control within a CMOS fabrication environment are being discussed.

Qualification of alternating PSM: defect inspection analysis in comparison to wafer printing results

With alternating phase shift masks (altPSM) an enhancement technique is available to realize smaller design rules. Meanwhile the basic production process for this mask type is well known and established for 193nm technology development. The qualification of the masks is now in the focus of development work. Sensitive defect inspection is essential for the qualification of altPSMs. In addition accurate phase and transmission balancing measurement technique has to be applied. In this paper we are presenting a detailed defect printability study for sub-100nm feature size technology at 193nm wavelength. Programmed quartz defects with different shapes and sizes were designed. They were implemented in a lines/spaces altPSM design. The processed quartz defects were characterized with a scanning electron microscope and an arial imaging microscope system. The printing behavior of the defects was analyzed after wafer exposures. In addition the required sensitivity for the altPSM inspection was evaluated. Finally the inspection sensitivity was characterized and optimized with programmed and production like defects.

Full-level alternating PSM for sub-100nm DRAM gate patterning

The lithographic potential of alternating PSM for sub-100nm gate patterning have been evaluated in comparison to alternative techniques. The status of the key elements of the full level alternating PSM approach including design conversion, optical proximity correction, mask making, double exposure and phase-shifting mask imaging will be demonstrated for a 256MDRAM device. Experimental data describing the phase-shifting mask quality, the lithographic process windows and the CD control obtained for alternating PSM in full level and array only approach will be presented.

Revival of grayscale technique in power semiconductor processing under low-cost manufacturing constraints

Grayscale lithography is a well-known technique for three dimensional structuring of a photo sensitive material. The 3D structuring of the photoresist is performed by a spatially variable exposure. Pixelated grayscale mask structures are defined to achieve the desired 3D resist patterns by locally variable transmittance values. Within power semiconductor processing, grayscale techniques could beneficially be applied in different process steps. Several ideas come to mind for process simplification, alternative integration scheme and more, e.g. the realization of 3D resist patterns for implant applications in order to control the doping depth and profiles and their influence on device parameters. In order to make the grayscale process useful for manufacturing of semiconductor devices it is necessary to master and consider the inherent process variability. Lithographic simulation is used to optimize the sub-resolution photo-mask features and to predict the final resist shape and its variability. Device simulation for a DMOS device, used in our 130nm technology node, shows that the device performance would benefit from an attenuation of the implant dose in the center of the device, which could be achieved by creating a resist island with reduced resist thickness in the center of the drawn implant opening of the DMOS device. In order to achieve the desired target geometry of the implant resist mask, simulations with Sentaurus Lithography have been performed resulting in a suitable mask design and lithographic process. We will demonstrate the development of the grayscale litho-process based on the needs of an implant scheme that is going to be used for a DMOS device, with respect to process stability and achieved resist mask dimensions.

Rigorous wafer topography simulation for investigating wafer alignment quality and robustness

We have been utilizing rigorous simulation software in order to predict the alignment mark signal quality and mark contrast variation induced by processes changes reliably. We have run simulations in order to understand which parameters influence alignment mark quality most and to determine the important parameters that can be manipulated in order to improve it. Simulation of alignment signals (also referred to as waveforms) has been done for resist marks and etched marks, coated and uncoated, as well as in presence of increasing topography complexity. To validate simulation analysis, mark signal collection for different processes (and/or variations of those) and products has been carried out; cross sections have also been generated.

Hard phase-shifting masks for the 65-nm node: a performance comparison

The lithographic potential of various mask types for the printing of 65nm features has been investigated by simulation and experimentation. As key parameters process window, mask error enhancement factor, balancing performance, and phase and CD error susceptibility have been analyzed. Alternating chromeless phase-shifting masks (PSM) show the smallest mask error enhancement factor (MEEF), but the largest phase and CD error sensitivity. Alternating PSM have a larger MEEF but require less tight mask specifications. Double edge chromeless PSM combine small MEEF value with relaxed phase and CD control specifications when an appropriate illumination is chosen. Good intra-field CD control and sufficient large process window for 65nm pattern can be obtained for this mask type. The impact of aberrations and pupil imperfections on the CD control has been investigated. The mask processes will be discussed and mask performance data introduced.