Niladri N. Mojumder

A Three-Terminal Dual-Pillar STT-MRAM for High-Performance Robust Memory Applications

The design of a three-terminal self-aligned dual-pillar (DP) magnetic tunnel junction (MTJ) utilizing both current-induced spin-transfer torque (STT) and magnetic domain-wall motion effects is proposed for high-speed nonvolatile robust memory applications. The choice of a thin tunneling oxide (~0.9 nm) in a write-in port, spatially and electrically separated from a read-out port incorporating a thicker (~1.8 nm) oxide on an extended thin-film multilayer stack, significantly improves the overall cell stability and parametric process yield of a memory array. A dual-bit-line memory architecture incorporating a single-ended voltage-sensing scheme for fast data readout with just one access transistor per cell is also proposed for the first time. The technology-circuit cooptimization of the proposed single-transistor (1T) DP STT magnetic random access memory (MRAM) cell is carried out using effective mass-based transport simulations in nonequilibrium Greens function formalism and accurate micromagnetic simulations involving the Landau-Lifshitz-Gilbert-Slonczewski equation. The proposed DP STT-MRAM bit cell outperforms a state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell tunneling magnetoresistance, simplified memory array architecture with a single supply for read/write, and significantly lower probability of disturb and access failures under parametric process variations with a marginal increase in critical switching current.

KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells

The storage device in spin-transfer torque MRAM (STT-MRAM) is the magnetic tunneling junction (MTJ) and several models for the MTJ have been proposed. However, a simulation framework that captures device physics at the atomistic level when simulating STT-MRAM at the bit-cell level is lacking. We propose a simulation framework (KNACK) which models the MTJ at the atomistic level using the Non-Equilibrium Greens Function (NEGF) formalism and uses the NEGF model in conjunction with our STT-MRAM bit-cell circuit model for circuit-level simulations. Our simulation framework accepts I–V and C-V characteristics of the access device input either as lookup tables or as compact models. We show that with appropriate device and bit-cell parameters, our simulation framework has the ability to capture MTJ physics and simulate different genres of STT-MRAM bit-cells with results in agreement with experiments.

Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture

Spin-transfer torque magnetic RAM (STT MRAM) has emerged as a promising candidate for on-chip memory in future computing platforms. We present a cross-layer (device-circuit-architecture) approach to energy-efficient cache design using STT MRAM. At the device and circuit levels, we consider different genres of MTJs and bitcells, and evaluate their impact on the area, energy and performance of caches. In addition, we propose microarchitectural techniques viz. sequential cache read and partial cache line update, which exploit the non-volatility of STT MRAM to further improve energy efficiency of STT MRAM caches. A detailed comparison of STT MRAM caches with SRAM-based caches is also presented. Our results indicate that the proposed optimizations significantly enhance the efficiency of STT MRAM for designing lower level caches.

Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective

Electron-spin based data storage for on-chip memories has the potential for ultrahigh density, low power consumption, very high endurance, and reasonably low read/write latency. In this article, we analyze the energy-performance characteristics of a state-of-the-art spin-transfer-torque based magnetic random access memories (STT-MRAM) bit-cell in the presence of parametric process variations. In order to realize ultra low power under process variations, we propose device, bit-cell and architecture level design techniques. Such design methods at various levels of design abstraction has been found to achieve substantially enhanced robustness, density, reliability and low power as compared to their charge-based counterparts for future embedded applications.

Layout-aware optimization of STT MRAMs

We present a layout-aware optimization methodology for spin-transfer torque (STT) MRAMs, considering the dependence of cell area on the access transistor width (WFET), number of fingers in the access transistor and the metal pitch of bit- and source-lines. It is shown that for WFET less than a critical value (~7 times the minimum feature length), one-finger transistor yields minimum cell area. For large WFET, minimum cell area is achieved with a two-finger transistor. We also show that for a range of WFET, the cell area is limited by the metal pitch of bit- and source-lines. As a result, in the metal pitch limited (MPL) region, WFET can be increased with no change in the cell area. We analyze the impact of increase in WFET in the MPL region on the write margin and cell tunneling magneto-resistance (CTMR) of different genres of STT MRAMs. We consider conventional STT MRAM cells in the standard and reverse-connected configurations and STT MRAMs with tilted magnetic anisotropy for the analysis. By increasing WFET from the minimum to the maximum value in the MPL region (at iso-cell area) and reducing read voltage to achieve iso-read disturb margin, 2X improvement in write margin and 27% improvement in CTMR is achieved for the reverse-connected STT MRAM. Similar trends are observed for other STT MRAM cells.

Band-to-Band Tunneling Ballistic Nanowire FET: Circuit-Compatible Device Modeling and Design of Ultra-Low-Power Digital Circuits and Memories

Band-to-band tunneling (BTBT) nanowire FETs have been studied as a possible successor to CMOS FETs. In the literature, it has already been shown that a 1-D p+-i- n+-type semiconductor nanowire governed by a BTBT transport mechanism offers a subthreshold swing lower than the conventional limit of 60 mV/dec while maintaining a reasonable on-state performance. The concept of BTBT nanowire FETs is primitive, and the manufacturing process is nascent. In the absence of a suitable device model and/or a reliable circuit simulator, the evaluation and impact of such novel transistors are difficult to estimate. In this paper, we propose a simple complementary device model for BTBT nanowire FETs suitable for multitransistor circuit simulation and evaluate its performance in the ballistic limit. The device models so developed have been used to simulate a class digital logic circuits and dynamic memories (e.g., DRAM) to analyze their suitability in future very large scale integration design. Circuit level simulations explicitly show that the proposed p+ -i-n+-type BTBT nanowire FETs are well suited for medium throughput (approximately hundreds of kilohertz to a few tens of megahertz) ultra-low-power applications. The standby leakage power in memory and logic circuits has been found to be as low as 10-20 W due to the inherent super cutoff nature of the device. The presence of interconnect parasitics in parallel with intrinsic device capacitance severely limits the performance of digital circuits. The impact of interconnect parasitics on the performance of BTBT nanowire FETs has also been studied.

Effect of quantum confinement on spin transport and magnetization dynamics in dual barrier spin transfer torque magnetic tunnel junctions

Electronic transport and magnetization dynamics associated with the current induced spin torque effects in dual barrier magnetic tunnel junctions (MTJs) have been investigated using nonequilibrium Green’s Function equations solved self-consistently with Landau–Lifshitz–Gilbert–Slonczewski equation. In a dual barrier (pentalayer) MTJ, a set of geometry and band-structure parameters jointly determines the position of resonant peaks and valleys within the energy range of interest. The presence of nonmonotonic quantum well states inside the central ferromagnetic free layer significantly modifies the critical switching voltage across MTJ and tunneling magnetoresistance simultaneously depending on whether the resonant condition is satisfied. Proper choice of (i) free ferromagnetic layer thickness, (ii) tunneling barrier height, (iii) width of the tunneling barrier, and (iv) operational voltage has been found to increase both in-plane and out-of-plane spin torque efficiencies in pentalayer MTJs by approximately ...

Magnonic Spin-Transfer Torque MRAM With Low Power, High Speed, and Error-Free Switching

A new class of spin-transfer torque magnetic random access memory (STT-MRAM) is discussed, in which writing is achieved using thermally initiated magnonic current pulses as an alternative to conventional electric current pulses. The magnonic pulses are used to destabilize the magnetic free layer from its initial direction, and are followed immediately by a bipolar electric current exerting conventional spin-transfer torque on the free layer. The combination of thermal and electric currents greatly reduces switching errors, and simultaneously reduces the electric switching current density by more than an order of magnitude as compared to conventional STT-MRAM. The energy efficiency of several possible electro-thermal circuit designs have been analyzed numerically. As compared to STT-MRAM with perpendicular magnetic anisotropy, magnonic STT-MRAM reduces the overall switching energy by almost 80%. Furthermore, the lower electric current density allows the use of thicker tunnel barriers, which should result in higher tunneling magneto-resistance and improved tunnel barrier reliability. The combination of lower power, improved reliability, higher integration density, and larger read margin make magnonic STT-MRAM a promising choice for future non-volatile storage.

Proposal for Switching Current Reduction Using Reference Layer With Tilted Magnetic Anisotropy in Magnetic Tunnel Junctions for Spin-Transfer Torque (STT) MRAM

The design and statistical analysis of a magnetic tunnel junction with pinned-layer uniaxial anisotropy, slightly tilted with respect to the perpendicular magnetic anisotropy (PMA) of the free layer, are presented in the presence of thermally induced magnetic noise. The marginal tilting of the pinned-layer easy axis reduces the critical switching current density by almost 80%, as compared to a regular PMA device for a delay of 2 ns with a switching failure probability lower than 10-9. Substantially lower switching current density in spin-transfer torque MRAM with tilted pinned-layer anisotropy enables the use of a higher resistance-area product with a thicker tunnel barrier that compensates for the tunneling-magnetoresistance rolloff due to the relative misalignment of free- and pinned-layer easy axes.

STT-MRAMs for future universal memories: Perspective and prospective

Electron-spin based data storage for on-chip memories has the potential for ultra-high density, low-power consumption, very high endurance, and reasonably low read/write latency. In this article, we analyze the energy-performance characteristics of a state-of-the-art spin-transfer-torque based magnetic random access memories (STT-MRAM) bit-cell in the presence of parametric process variations. In order to realize ultra low power under process variations, we propose device and bit-cell level design techniques. Such design methods at various levels of design abstraction has been found to achieve substantially enhanced robustness, density, reliability and low power as compared to their charge-based counterparts for future embedded applications.