Niyaz Khusnatdinov

High-throughput jet and flash imprint lithography for advanced semiconductor memory

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography (J-FIL) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Non-fill defectivity must always be considered within the context of process throughput. Processing steps such as resist exposure time and mask/wafer separation are well understood, and typical times for the steps are on the order of 0.10 to 0.20 seconds. To achieve a total process throughput of 20 wafers per hour (wph), it is necessary to complete the fluid fill step in 1.0 seconds, making it the key limiting step in an imprint process. Recently, defect densities of less than 1.0/cm2 have been achieved at a fill time of 1.2 seconds by reducing resist drop size and optimizing the drop pattern. There are several parameters that can impact resist filling. Key parameters include resist drop volume (smaller is better), system controls (which address drop spreading after jetting), Design for Imprint or DFI (to accelerate drop spreading) and material engineering (to promote wetting between the resist and underlying adhesion layer). In addition, it is mandatory to maintain fast filling, even for edge field imprinting. This paper addresses the improvements made with reduced drop volume and enhanced surface wetting to demonstrate that fast filling can be achieved for both full fields and edge fields. By incorporating the changes to the process noted above, we are now attaining fill times of 1 second with non-fill defectivity of ~ 0.1 defects/cm2.

Nanoscale magnification and shape control system for precision overlay in jet and flash imprint lithography

Jet and flash imprint lithography steppers have demonstrated unprecedented capability for patterning of sub-25-nm features for semiconductor manufacturing. A critical requirement for such patterning is the ability to overlay one layer of a device to a previously printed layer. In this paper, the design and development of a nanoprecision mask magnification/shape control system (MSCS) for the unique requirements of imprint-based overlay is presented. Imprint specific topics such as in-liquid overlay and distortions, and on-tool overlay metrology are discussed. The MSCS presented here has demonstrated 10-nm mix and match overlay (mean + 3 sigma) capability that approaches performance of state-of-the-art photolithography tools.

High throughput Jet and Flash Imprint Lithography for semiconductor memory applications

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are two critical components to meeting throughput requirements for imprint lithography. Using a similar approach to what is already done for many deposition and etch processes, imprint stations can be clustered to enhance throughput. The FPA-1200NZ2C is a four station cluster system designed for high volume manufacturing. For a single station, throughput includes overhead, resist dispense, resist fill time (or spread time), exposure and separation. Resist exposure time and mask/wafer separation are well understood processing steps with typical durations on the order of 0.10 to 0.20 seconds. To achieve a total process throughput of 15 wafers per hour (wph) for a single station, it is necessary to complete the fluid fill step in 1.5 seconds. For a throughput of 20 wph, fill time must be reduced to only one second. There are several parameters that can impact resist filling. Key parameters include resist drop volume (smaller is better), system controls (which address drop spreading after jetting), Design for Imprint or DFI (to accelerate drop spreading) and material engineering (to promote wetting between the resist and underlying adhesion layer). In addition, it is mandatory to maintain fast filling, even for edge field imprinting. In this paper, we address the improvements made in all of these parameters to enable a 1.50 second filling process for a sub-20nm device like pattern and have demonstrated this capability for both full fields and edge fields.

Linewidth roughness characterization in step and flash imprint lithography

Despite the remarkable progress made in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template (imprint mask). As a high fidelity replication process, the resolution of imprint lithography is determined by the ability to create a master template having the required dimensions. Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. Non chemically amplified resists, such as ZEP520A, are not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the final patterned substrate. Three experiments were performed documenting LWR in the template, imprint, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3σ), and independent of the processing step and feature size.

Fabrication of nano and micro optical elements by step and flash imprint lithography

The Step and Flash Imprint Lithography (S-FILTM) process is a step and repeat nano-imprint lithography (NIL) technique based on UV curable low viscosity liquids.1,2,3Investigation by this group and others has shown that the resolution of replication by imprint lithography is limited only by the size of the structures that can be created on the template (mold). S-FIL uses field-to-field drop dispensing of UV curable liquids for step and repeat patterning. This approach allows for micro and nano-fabrication of devices with widely varying pattern densities and complicated structures. Wire grid polarizers and micro lenses are two examples for optical components that can be formed using SFIL technology. Step and Flash Imprint Lithography Reverse (S-FIL/R) tone has been used to form resist patterns for a number of different device types 1,4,6. The authors have employed S-FIL/R and dry develop techniques to form resist patterns with 100 nm period useful for the fabrication of wire grid polarizers. S-FIL/R has a number of advantages over interference lithography techniques for the fabrication of sub 200 nm period grating structures including but no limited to pattern repeatability, vibration insensitivity, high aspect ratio feature formation, greater extendibility and high resolution. The authors have devised imprint and dry etching processes for resist and substrate patterning to form Al based wire grid polarizers with 100 nm pitch. The fabrication processes and resulting devises will be described. While S-FIL is useful for in the formation of resist patterned wafers, it is also capable of forming devices by functional material patterning. Polymer micro lenses are a good examples of functional material devices useful for a number of applications including CMOS and CCD cameras. The fact that lens geometry is defined by the template and requires no post imprint processing provides a strong advantage over current lens formation approaches. Recent results and the state of current micro lens fabrication by S-FIL is described.

Controlling linewidth roughness in step and flash imprint lithography

Despite the remarkable progress made in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template (imprint mask). As a high fidelity replication process, the resolution of imprint lithography is determined by the ability to create a master template having the required dimensions. Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. Non chemically amplified resists, such as ZEP520A, are not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the final patterned substrate. Three experiments were performed documenting LWR in the template, imprint, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3σ), and independent of the processing step and feature size.

A novel resist system for enhanced resist spreading in nanoimprint lithography

Imprint lithography is a promising technology for replication of nano-scale features. For semiconductor device applications, Canon deposits a low viscosity resist on a field by field basis using jetting technology. A patterned mask is lowered into the resist fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are two critical components to meeting throughput requirements for imprint lithography. The first component uses a similar approach to what is already done for many deposition and etch processes. Imprint stations can be clustered to enhance throughput. The FPA-1200NZ2C is a four station cluster system designed for high volume manufacturing. The second component is resist fill. For a single station, throughput includes overhead, resist dispense, resist fill time, exposure and separation. Resist exposure time and mask/wafer separation are well understood processing steps with typical durations on the order of 0.10 to 0.20 seconds. To achieve a total process throughput of 20 wafers per hour (wph) for a single station (or 80 wph for a four station NZ2C system), it is necessary to complete the fluid fill step in 1.1 seconds. There are several parameters that can impact resist filling. Key parameters include resist drop volume (smaller is better), system controls (which can impact spreading after jetting), Design for Imprint or DFI (to accelerate drop merging) and material engineering (to promote drop spreading after dispense). In addition, it is mandatory to maintain fast filling, even for edge field imprinting. In this paper, we address the improvements made in DFI and material engineering. By optimizing the drop pattern layout and introducing a two component resist system that enhances resist spreading, throughputs of 80 wafers per hour or more are achieved.

Inkjet-based adaptive planarization (Conference Presentation)

Planarization is a critical unit step in the lithography process because it enables patterning of surfaces with versatile pattern density without compromising on the stringent planarity and depth-of-focus requirements. In addition to nanoscale pattern density variation, parasitics such as pre-existing wafer topography, can corrupt the desired process output after planarization. The topography of any surface can be classified in three broad categories, depending upon the amplitude and spatial wavelength of the same [1], [2]: (i) nominal shape, (ii) nanotopography and (iii) roughness. The nominal shape is given by the largest spatial wavelengths, typically < 20mm. For spatial length scales of ~1-20mm, height variations at this spatial wavelength range are classified as nanotopography. Roughness usually has lower spatial wavelengths. While the nominal shape of a substrate surface is usually decided by the nature of wafer preparation and the tooling and chucking infrastructure used in the same, roughness is usually mitigated by standard polishing techniques. It is the intermediate nanotopography that is probably the most critical surface topography parameter. This is because most traditional polishing techniques cannot selectively address pre-existing substrate topography, without introducing a parasitic signature at the scale of nanotopography. Moreover, fields with pattern density variation typically also have length scales that are commensurate with nanotopography. It is thus instructive to summarize existing planarization technology to understand current limitations. Spin on Glass and Etch back is one technique used for micron scale device manufacturing [3]. As the name implies, a glass dielectric is spin-coated on the substrate followed by etching in a chemistry that ensures equal etching rates for both the sacrificial glass and the underlying film or substrate material. Photoresists may also be used instead of glass. However, the global planarity that can be achieved by this technique is limited. Also, planarization over a large isolated topographical feature has been studied for the reverse-tone Jet-and-Flash Imprint Lithography process, also known as JFIL-R [4]. This relies on surface tension and capillary effects to smoothen a spin-coated Si containing film that can be etched to obtain a smooth profile. To meet the stringent requirement of planarity in submicron device technologies Chemical Mechanical Planarization (CMP) is the most widely used planarization technology [5], [6]. It uses a combination of abrasive laden chemical slurry and a mechanical pad for achieving planar profiles. The biggest concern with CMP is the dependence of material removal rate on the pattern density of material, leading to the formation of a step between the high density and low-density. The step shows up as a long-range thickness variation in the planarized film, similar in scale to pre-existing substrate topography that should have been polished away. Preventive techniques like dummy fill and patterned resist can be used to reduce the variation in pattern density. These techniques increase the complexity of the planarization process and significantly limit the device design flexibility. Contact Planarization (CP) has also been reported as an alternative to the CMP processing [7], [8]. A substrate is spin coated with a photo curable material and pre baked to remove residual solvent. An ultra-flat surface or an optical flat is pressed on the spin-coated wafer. The material is forced to reflow. Pressure is used to spread out material evenly and achieve global planarization. The substrate is then exposed to UV radiation to harden the photo curable material. Although attractive, this process is not adaptive as it does not account for differences in surface topography of the wafer and the optical flat, nor can it address all the parasitics that arise during the process itself. The optical flat leads to undesirable planarization of even the substrate nominal shape and nanotopography, which corrupts the final film thickness profile. Hence, it becomes extremely difficult to eliminate this signature to a desirable extent without introducing other parasitic signatures. An example of this is shown in Figure 1. In this paper, a novel adaptive planarization process has been presented that potentially addresses the problems associated with planarization of varying pattern density, even in the presence of pre-existing substrate topography [9]. This process is called Inkjet-enabled Adaptive Planarization (IAP). The IAP process uses an inverse optimization scheme, built around a validated fluid mechanics-based forward model [10], that takes the pre-existing substrate topography and pattern layout as inputs. It then generates an inkjet drop pattern with a material distribution that is correlated with the desired planarization film profile. This allows a contiguous film to be formed with the desired thickness variation to cater to the topography and any parasitic signatures caused by the pattern layout. This film is formed by the coercing action of a compliant superstrate, which forces the drops to spread and merge and eliminates any bubble trapping. Then, the film is cured using blanket UV exposure and the superstrate separated to reveal the desired planarized film. The use of an inverse optimization algorithm allows substrate topography to be addressed adaptively. In other words, the algorithm can generate a drop pattern that does not disturb the pre-existing substrate topography substantially, but only caters to the pattern density variation. This process has potential advantages over other planarization techniques because of its adaptive nature. Hence, the IAP process can cater to substrates of varying topographies and pattern densities by changing the inkjetted material distribution, without any changes in hardware. The IAP process can also address pre-existing substrate topography selectively by conforming to the nominal shape while planarizing over the pattern layout. A schematic of the IAP process is shown in Figure 2. The goal of this paper is to present some preliminary results from the IAP process. A test pattern layout has been generated with the help of photolithography, and is shown in Figure 3. For the purpose of this trial, the nanoscale features have not been patterned, as it is expected that the planarization process will be blind to their presence. Thus, areas with nanoscale patterns have been patterned as a single feature of SiO2 with height equal to 100 nm. These features are adjacent to pattern-less areas, thus marking a drastic change in pattern density. As can be seen in Figure 4, the smallest length scale across which pattern density changes, is 70 microns. The goal of the IAP process is to be able to planarize this pattern with a film that conforms to pre-existing substrate topography. The targeted planarity of the film is 95% 3sigma, while the targeted film thickness at the tallest feature is less than 30 nm. In another trial, the inverse tone of the same layout will also be tested. This pattern has features of height equal to 100 nm where the previous pattern did not. The targeted metrics for the inverse layout are the same as the nominal layout.

Development of a robust reverse tone pattern transfer process

Pattern transfer is critical to any lithographic technology, and plays a significant role in defining the critical features in a device layer. As both the memory and logic roadmaps continue to advance, greater importance is placed on the scheme used to do the etching. For many critical layers, a need has developed which requires a multilayer stack to be defined in order to perform the pattern transfer. There are many cases however, where this standard approach does not provide the best results in terms of critical dimension (CD) fidelity and CD uniformity. As an example, when defining a contact pattern, it may be advantageous to apply a bright field mask (in order to maximize the normalized inverse log slope (NILS)) over the more conventional dark field mask. The result of applying the bright field mask in combination with positive imaging resist is to define an array of pillar patterns, which then must be converted back to holes before etching the underlying dielectric material. There have been several publications on tone reversal that is introduced in the resist process itself, but often an etch transfer process is applied to reverse the pattern tone. The purpose of this paper is to describe the use of a three layer reverse tone process (RTP) that is capable of reversing the tone of every printed feature type. The process utilizes a resist pattern, a hardmask layer and an additional protection layer. The three layer approach overcomes issues encountered when using a single masking layer. Successful tone reversal was demonstrated both on 300mm wafers and imprint masks, including the largest features in the pattern, with dimensions as great as 60 microns. Initial in-field CD uniformity is promising. CDs shifted by about 2.6nm and no change was observed in either LER or LWR. Follow-up work is required to statistically qualify in-field CDU and also understand both across wafer uniformity and feature linearity.

High throughput nanoimprint lithography for semiconductor memory applications

Imprint lithography is a promising technology for replication of nano-scale features. For semiconductor device applications, Canon deposits a low viscosity resist on a field by field basis using jetting technology. A patterned mask is lowered into the resist fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are two critical components to meeting throughput requirements for imprint lithography. Using a similar approach to what is already done for many deposition and etch processes, imprint stations can be clustered to enhance throughput. The FPA-1200NZ2C is a four station cluster system designed for high volume manufacturing. For a single station, throughput includes overhead, resist dispense, resist fill time (or spread time), exposure and separation. Resist exposure time and mask/wafer separation are well understood processing steps with typical durations on the order of 0.10 to 0.20 seconds. To achieve a total process throughput of 17 wafers per hour (wph) for a single station, it is necessary to complete the fluid fill step in 1.2 seconds. For a throughput of 20 wph, fill time must be reduced to only one 1.1 seconds. There are several parameters that can impact resist filling. Key parameters include resist drop volume (smaller is better), system controls (which address drop spreading after jetting), Design for Imprint or DFI (to accelerate drop spreading) and material engineering (to promote wetting between the resist and underlying adhesion layer). In addition, it is mandatory to maintain fast filling, even for edge field imprinting. In this paper, we address the improvements made in all of these parameters to first enable a 1.20 second filling process for a device like pattern and have demonstrated this capability for both full fields and edge fields. Non-fill defectivity is well under 1.0 defects/cm2 for both field types. Next, by further reducing drop volume and optimizing drop patterns, a fill time of 1.1 seconds was demonstrated.