Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Nobukazu Ito is active.

Publication


Featured researches published by Nobukazu Ito.


Optical Engineering | 2006

New thermally isolated pixel structure for high-resolution (640×480) uncooled infrared focal plane arrays

Shigeru Tohyama; Masaru Miyoshi; Seiji Kurashina; Nobukazu Ito; T. Sasaki; Akira Ajisawa; Yutaka Tanaka; Akihiro Kawahara; Kiyoshi Iida; Naoki Oda

A new pixel structure with twice-bent beams and eaves structure, suitable for high-resolution uncooled infrared (IR) focal plane arrays (FPAs), is proposed. In comparison with previous results (FPA of 37-µm pixel pitch), the thermal conductance of the test device with the proposed pixel structure of 23.5-µm pitch is reduced about 2.5 times. The eaves structure, which is adopted to increase the fill factor of pixels, improves the responsivity by a factor of 1.3. A 640×480 bolometer-type uncooled IRFPA is demonstrated by utilizing the new pixel structure, with supplementary modification to improve thermal conductance and thermal time constant. It shows a noise equivalent temperature difference (NETD) of 50 mK for F/1.0 optics at 30 frames/sec, a thermal conductance of 0.03 µW/K, and a thermal time constant of 16 msec.


Infrared Technology and Applications XXX | 2004

New thermally isolated pixel structure for high-resolution uncooled infrared FPAs

Shigeru Tohyama; Masaru Miyoshi; Seiji Kurashina; Nobukazu Ito; T. Sasaki; Akira Ajisawa; Naoki Oda

This paper proposes a new thermally isolated pixel structure, having a twice-bent beam structure and eaves structure, suitable for high-resolution uncooled infrared (IR) focal-plane arrays (FPAs). It also describes the properties of test devices, fabricated to verify the effect of the new pixel structure. Although the pixel size of the test devices is 23.5 μm × 23.5 μm, which represents a smaller area by a factor of about 2.5 than the 37 μm × 37 μm pixel size for the 320 × 240 bolometer-type uncooled IRFPA, previously developed by the authors, the test devices have beams with almost the same length as in the previous IRFPA by utilizing the new beam structure. In addition, the cross-sectional area of the beam is reduced. Accordingly, the thermal conductance of the test devices can be reduced by a factor of about 2.5. The eaves structure, which is adopted to increase the fill factor of pixels, improves the responsivity by a factor of 1.3, which is consistent with our calculations. By utilizing the new thermally isolated pixel structure, the test devices with 23.5 μm pixels enable us to achieve thermal sensitivity equivalent to the previous 37 μm pixels.


international symposium on semiconductor manufacturing | 2001

Development of a two-step electroplating process with a long-term stability for applying to Cu metallization of 0.1-/spl mu/m generation logic ULSIs

Koji Arita; Nobukazu Ito; Nobuki Hosoi; Hidenobu Miyamoto

Developed a two-step copper (Cu) electroplating (EP) process using a seed-enhancement step with an alkali-metal-free Cu-pyrophosphate solution. The solution for the seed-enhancement step has low solubility of Cu compared with conventional Cu-sulfate solution and high macrothrowing power. As a result, the two-step EP solution provided a superior seed-enhancement effect and filling properties compared to conventional Cu sulfate EP. The seed-enhancement solution has excellent long-term stability of each components concentration, and there is no change of process performance over a two-month period. The authors can easily control sheet resistance (Rs) of electroplated films which correlates with thickness and nonuniformity of seed-enhancement films with no maintenance other than the addition of de-ionized (DI) water to compensate for evaporated water. The two-step EP process achieved an excellent via-chain yield and a tight distribution of electromigration (EM) lifetime compared with the conventional EP process. Thus, the two-step EP process is a promising process for manufacturing technique of 0.1-/spl mu/m generation and beyond logic LSIs.


Archive | 1991

METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING AN AL/TIN/TI CONTACT

Nobukazu Ito


Archive | 1994

Process of manufacturing a semiconductor device by filling a via hole in an interlayered film of the device with wiring metal

Yoshiaki Yamada; Nobukazu Ito; Kuniko Miyakawa; Michiko Yamanaka


Archive | 1999

Method of forming multi-level copper interconnect with formation of copper oxide on exposed copper surface

Nobukazu Ito; Yoshihisa Matsubara


Archive | 2001

Process for manufacturing semiconductor device and exposure mask

Yoshihisa Matsubara; Kazumi Sugai; Nobukazu Ito; Kazuyoshi Ueno


Archive | 1999

Method of improving the planarization of wiring by CMP

Kazumi Sugai; Nobukazu Ito; Hiroaki Tachibana


Archive | 2005

Integrated circuit device, method of manufacturing the same and method of forming vanadium oxide film

Naoyoshi Kawahara; Hiroshi Murase; Hiroaki Ohkubo; Yasutaka Nakashiba; Naoki Oda; T. Sasaki; Nobukazu Ito


Archive | 2005

Integrated circuit including a temperature monitor element and thermal conducting layer

Hiroaki Ohkubo; Yasutaka Nakashiba; Naoyoshi Kawahara; Hiroshi Murase; Naoki Oda; T. Sasaki; Nobukazu Ito

Collaboration


Dive into the Nobukazu Ito's collaboration.

Researchain Logo
Decentralizing Knowledge