Naoyoshi Kawahara

Tradeoff Characteristics Between Resistivity and Reliability for Scaled-Down Cu-Based Interconnects

We investigated tradeoff characteristics between resistivity and reliability for scaled-down Cu-based interconnects. A unique resistivity-measurement technique is proposed to detect influences due to impurity doping. Using this technique, we investigated the impacts of the impurity doping on three types of copper interconnects - cobalt-tungsten-phosphorous (CoWP) metal-cap interconnects, plasma-enhanced chemical-vapor-deposition self-aligned barrier interconnects, and CuAl alloy interconnects - and clarified the tradeoffs between the resistivity and the reliability. We found that the metal-cap interconnect shows not only high reliability but also outstanding efficiency with regard to the suppression of resistance increase due to impurity doping.

Electromigration Lifetime Enhancement of CoWP Capped Cu Interconnects by Thermal Treatment

In order to develop highly reliable Cu interconnects, temperature dependence of the electromigration (EM) lifetime of metal (CoWP) capped Cu interconnects is investigated. It is found that the EM lifetime is enhanced as the test temperature rise from 275 to 380 °C. NH3 plasma treatment before the dielectric cap layer deposition on the CoWP capped Cu interconnects influenced the temperature dependence of EM lifetime, that is, the interconnects without the NH3 plasma treatment have longer EM lifetime than those with the NH3 plasma treatment at the higher test temperatures. In order to investigate the mechanism for this lifetime enhancement, micro-analysis and failure mode analysis were carried out. It is concluded that the Co alloying with Cu and the CoWP coverage repair due to Co diffusion at the high temperature lead to the EM lifetime enhancement.

Time-Dependent Dielectric Breakdown Characterization of 90- and 65-nm-Node Cu/SiOC Interconnects with Via Plugs

As the wiring-space decreases, the time-dependent dielectric breakdown (TDDB) of Cu/low-dielectric constant (k) interconnects becomes a critical reliability issue and more accurate prediction of the TDDB lifetime will be required. In this investigation, TDDB dependences on temperature and electric field are studied comprehensively for 90- and 65-nm-node Cu/SiOC interconnects using practical multilevel test structures with via plugs. Low-electric-field TDDB tests down to 1 MV/cm were carried out by a package TDDB method with high temperature up to 300 °C. Linear dependence of the TDDB lifetime on the electric-field is observed down to 1 MV/cm, and this suggests that the lifetime can be predicted using the E-model. The linear dependence of the TDDB lifetime on temperature is also observed up to 300 °C at 1.8 MV/cm. The activation energies for the 90 and 65 nm nodes are almost the same values, 0.76 eV for the 90 nm node and 0.74 eV for the 65 nm node. Failure is observed at the interfaces between the cap dielectric (SiCN) and the silicon dioxide layer with a surface polished by chemical-mechanical polishing (CMP) for both nodes. It is noted that no difference in the failure modes is seen between dense SiOC for the 90 nm node and porous SiOC for the 65 nm node, in spite of the different materials used for the intermetal dielectrics. This suggests that the polished interfaces greatly affect on the TDDB lifetime for both nodes. Improved TDDB lifetime is obtained by increasing the post-CMP cleaning time and the pretreatment time before the cap dielectric deposition. Sufficient TDDB lifetimes of over 10 years under practical operating conditions are obtained for both 90- and 65-nm-node Cu/low-k interconnects with via plugs.