Yasutaka Nakashiba

A face-to-face chip stacking 7kV RMS digital isolator for automotive and industrial motor drive applications

A face-to-face chip stacking isolator structure, which makes it easy to enhance the insulation voltage, is proposed. Transmitter (Tx) and receiver (Rx) chips, each of which has a coil, are stacked and communicate through a magnetic coupling of the coils. The die attach film sandwiched by the two chips not only bonds the chips but also enhances the insulation voltage by taking advantage of its thickness. With test chips, the breakdown voltage of 7 kV RMS is demonstrated and >20-year lifetime with a working voltage of 1.5 kV is estimated by extrapolation of time-dependent dielectric breakdown results.

Optimization of metal layers and substrate loss for the 3D solenoid structure inductors

This paper describes the optimization method on choice of the metal layers and the Si substrate structure about the 3-Dimantional(3D) vertical solenoid inductor on the CMOS process. The optimization of metal layers that constituted 3D structure inductors enable inductors, in which the two layers (Al, M6) stacked structure with area ratio of 0.3 and the three layers (Al, M6 and M5~M3) stacked structure with area ratio of 0.17, in comparison with an octagonal planer inductor. In spite of the reduction of area, the peak Q-factor on the inductor is almost equal. As for the constitution under the 3D solenoid inductors, Q-factor of inductor with PGS was lower than that of inductor without PGS, in the case of inductance <;1nH. Furthermore, the self-resonant frequency(fSR) of inductor without PGS was higher than that of inductor with PGS. As a result the inductor without PGS is available in a higher frequency domain than the inductor of PGS type.