Noel Poduje

Wafer Nanotopography Effects on CMP: Experimental Validation of Modeling Methods

Nanotopography refers to 10-100 nm surface height variations that exist on a lateral millimeter length scale on unpatterned silicon wafers. Chemical mechanical polishing (CMP) of deposited or grown films (e.g., oxide or nitride) on such wafers can generate undesirable film thinning which can be of substantial concern in shallow trench isolation (STI) manufacturability. Proper simulation of the effect of nanotopography on post-CMP film thickness is needed to help in the measurement, analysis, diagnosis, and correction of potential problems. Our previous work has focused on modeling approaches that seek to capture the thinning and post-CMP film thickness variation that results from nanotopography, using different modeling approaches. The importance of relative length scale of the CMP process used (planarization length) to the length scale of the nanotopography on the wafer (nanotopography length) has been suggested. In this work, we report on extensive experiments using sets of 200 mm epi wafers with a variety of nanotopography signatures (i.e., different nanotopography lengths), and CMP processes of various planarization lengths. Experimental results indicate a clear relationship between the relative scales of planarization length and nanotopography length: when the planarization length is less than the nanotopography length, little thinning occurs; when the CMP process has a larger planarization length, surface height variations are transferred into thin film thickness variations. In addition to presenting these experimental results, modeling of the nanotopography effect on dielectric CMP processes is reviewed, and measurement data from the experiments are compared to model predictions. Results show a good correlation between the model prediction and the experimental data.

Approaching new metrics for wafer flatness: an investigation of the lithographic consequences of wafer non-flatness

Flatness of the incoming silicon wafer is one major contributor to the ultimate focusing limitation of modern exposure tools. Exposure tools are designed to chuck wafers without creating non-flatness and then use focus control to follow as closely as possible the chucked wafer front surface topography. The smaller size of the exposure slit in a step-and-scan exposure tool, as compared to the previous generation full-field stepper tool, helps minimize the impact of chucked wafer non-flat topography. However, to maintain high throughput and improve critical dimension uniformity (CDU) at sub-wavelength line-widths requires continuous improvement in the incoming silicon wafer flatness. In this paper we report extensive experimental results that review existing wafer flatness metrics and propose the addition of a new metric. The new metric emulates the scanning motion of exposure by integrating the defocus that each point on the wafer experiences during exposure. We show that this method is in better spatial agreement with measured defocus in step-and-scan exposure tools. Simple metrics of moving average (MA) defocus prediction analysis will be defined and shown to correlate very well to post exposure defocus data. These experiments were enabled by the creation of special 300-nm wafers by MEMC. These special wafers include sites with a wide variation in flatness. Prior to exposure the wafers were measured with a high-resolution optical flatness metrology tool (WaferSight by ADE) to obtain industry standard thickness variation (flatness) data. Incoming wafer flatness data is used to predict wafer suitability for lithography at the desired device geometry node (e.g., 90 nm). The flatness data was processed and characterized using both standard metrics (SFQR) and the new MA analysis. The relationship between the industry standard metric (SFQR) and similar metrics applied to MA analysis will be presented. Full two-dimensional maps are used to present spatial correlations and permit simple physical insights into the flatness data sets. Measurements of chucked wafer flatness were made on the same wafers using ASML TWINSCAN in-line metrology. These measurements correlate very well to thickness-based flatness. Un-chucked wafer flatness metrics (SFQR and MA) are shown to correlate well to post exposure defocus data when an appropriate site size is used. This result is discussed in relationship to the industry-accepted practice of specifying un-chucked wafer flatness. Lithography performance tests were made to prove the relevance of the different flatness metrics. The same special wafers are used for lithography performance tests. These tests achieve excellent correlation between post-exposure full-wafer focus control results and predictions based on both SFQ (industry standard) and MA re-mapping of the flatness data. The relationship between measured critical dimension (CD) and defocus is also explored. Point-by-point analysis of CD residual versus measured defocus data nicely follows a Bossung curve. We also show that residual CD values predicted from defocus correlate well with measured values. These experiments confirm the application of industry standard wafer flatness measurements to step-and-scan lithography when appropriately using current metrics. They also present the potential for improved metrics based on the MA defocus prediction analysis to help drive continuous improvement of wafer flatness for advanced step-and-scan lithography.

Nanotopography effects on chemical mechanical polishing for shallow trench isolation

Nanotopography is the nanometer-scale height variation that occurs over lateral millimeter length scales on unpatterned silicon wafers. This height variation can result in excess thinning of surface films during chemical mechanical polishing (CMP) of shallow trench isolation (STI) structures. The development of an accurate nanotopography CMP modeling and characterization procedure will allow for the proper diagnosis of potential problems due to wafer nanotopography in a given STI CMP process. In this work, a nanotopography modeling methodology is proposed which relates the length scale of nanotopography features to the length scale of the CMP process. A combined density/step-height polishing model indicates that when the nanotopography features occur over a range comparable to or shorter than the planarization length, appreciable thinning is predicted. A contact wear CMP model similarly shows that as the pad stiffness increases, film thinning also increases. These simulation results indicate that the effect of nanotopography on STI CMP may be a substantial concern.

Modeling and Mapping of Nanotopography Interactions with CMP

As the demand for planarity increases with advanced IC technologies, nanotopography has arisen as an important concern in shallow trench isolation (STI) chemical mechanical polishing (CMP) processes. Previous work has shown that nanotopography, or small surface height variations on raw wafers 20 to 50 nm in amplitude extending across millimeter scale lateral distances, can result in substantial CMP-induced localized thinning of surface films such as oxides or nitrides used in STI [1]. This interaction with CMP depends both on characteristics of the wafer such as heights and spatial wavelengths of the nanotopography, and characteristics of the CMP process including the planarization length or pad stiffness. In this paper we review and extend the previous work on modeling of nanotopography. Three approaches to predicting the post-CMP oxide thinning due to nanotopography are compared. The first approach is the simplest, where a statistical aggregate effect is computed. Following the work of Schmolke [2], a transfer coefficient α is found which captures the portion of the nanotopography that is correlated with the final oxide thinning. The second approach is the most detailed, depending on explicit numerical simulation of pad elastic properties. In this case, a contact wear simulation is used to produce a detailed map of oxide thickness corresponding to any given pre-measured nanotopography wafer surface. The third approach is a signal processing method, sitting somewhere between the previous two extremes in terms of approximation and complexity. In this last case, a two-dimensional transfer function is extracted which captures the spatial smoothing accomplished by CMP. This filter can then be applied efficiently to premeasured nanotopography maps for other wafers to predict the final oxide thicknesses. We also propose a predictive mapping of post-CMP oxide or nitride thicknesses to provide insight into the relative goodness of a wafer measured for nanotopography which is to be subjected to a CMP process. Specifically, we suggest that for post-CMP impact, maps and computation of areas having insufficient oxide clearing, or having final nitride thickness outside of required ranges, are useful and practical. Such device failure potential maps complement the fundamental nanotopography height map data and metrics based directly on that data, and enable evaluation, comparison, and development of improved wafers and STI CMP processes. I. Background Nanotopography refers to nanometer scale height variations that exist over lateral millimeter wavelengths on unpatterned silicon wafers, as illustrated in Fig. 1. Films deposited on wafers with certain nanotopography types have been shown to exhibit post-CMP film thinning, or localized deviation in the polished film thickness, with the relative length scales of the nanotopography and the CMP process serving as significant factors [3]. Wafer nanotopography effects are larger in single-sided polished wafers where the height variations are largest (~100 nm); these effects are also of concern in double-sided polished wafers but with smaller variation (~30 nm). Wafer nanotopography varies depending on the process used during raw wafer production, and can be characterized by both height and lateral extent of the surface height variation.

The Transition to Optical Wafer Flatness Metrology

As optical lithography requirements drive wafer flatness toward increasing levels of perfection, the industry is faced with a need to transition from current standard practice. In this paper we present a historical perspective on starting material dimensional metrology, leading to the current standard for wafer manufacturing quality control, capacitance‐based wafer flatness metrology. We then investigate the market and technical factors that compel a transition to optical flatness metrology. Comparative data (from advanced 300mm wafers) between capacitive and optical flatness measurement tools permits us to conclude that the industry transition to optical dimensional metrology can occur without disruption of accepted manufacturing baselines.