Jaydeep K. Sinha

Predicting distortions and overlay errors due to wafer deformation during chucking on lithography scanners

Chucking of substrates with wafer shape and thickness variations results in elastic deformation that can cause significant in-plane distortions that lead to overlay errors in lithographic patterning. As feature sizes shrink, overlay errors due to the combination of wafer geometry and chucking become a larger fraction of the error budget and must be controlled. We use a finite element model and a lithographic correction postprocessing scheme to predict in-plane distortions that result from chucking wafers with shape variations. We then use the predictions of in-plane distortions at two different patterning steps to calculate the component of overlay error that arises from localized shape variations. Using the model, in-plane distortion and overlay errors due to chucking are examined for multiple wafers with different geometries. The results show that long spatial wavelength shape variations cause significant distortion, but can largely be mitigated through the use of simple first-order corrections that are applied in typical lithography scanners. In contrast, high-frequency spatial variations cause distortions that cannot be corrected and hence lead to meaningful overlay errors. The results provide fundamental insight into chucking-induced overlay errors and can serve as a basis for the development of higher order scanner correction schemes that explicitly account for the wafer geometry through high-density wafer shape measurements.

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Abstract. Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Relationship between localized wafer shape changes induced by residual stress and overlay errors

The deposition of films with nonuniform residual stress can induce local changes in wafer shape and contribute to overlay errors with magnitudes that may be significant in advanced lithographic patterning processes. Understanding the fundamental relationship between residual stress, localized wafer shape changes, and overlay error is crucial for realizing new schemes to manage overlay errors, particularly at advanced nodes where feature sizes are smaller. In the present work, finite element modeling is used to quantitatively relate nonuniform residual stress in a deposited thin film to localized wafer shape changes and overlay errors. The results demonstrate that there is a strong correlation between localized shape variations induced by nonuniform residual stresses and noncorrectable overlay errors.

TSV metrology and inspection challenges

The interest in 3D packaging and specifically TSV processes has grown significantly in the past few years, with nearly every major chip manufacturer announcing plans to develop and implement this technology. As TSV process flows become stabilized, a number of metrology and inspection issues and opportunities have arisen. Many of these challenges are novel to the industry due to the relatively large size of the vias and new processes such as wafer back-grinding and carrier bonding. This paper summarizes the initial trial process monitoring that has been used during via-first TSV process development at IMEC. This process is designed for SiC (system in chip) applications, using Cu-filled vias measuring 5 um wide by 22 or 50 um deep. While there are a variety of metrology and inspection applications for TSV processing, the main topics covered here are via size measurement, post-grind wafer inspection, and carrier wafer bonding inspection.

Approaching new metrics for wafer flatness: an investigation of the lithographic consequences of wafer non-flatness

Flatness of the incoming silicon wafer is one major contributor to the ultimate focusing limitation of modern exposure tools. Exposure tools are designed to chuck wafers without creating non-flatness and then use focus control to follow as closely as possible the chucked wafer front surface topography. The smaller size of the exposure slit in a step-and-scan exposure tool, as compared to the previous generation full-field stepper tool, helps minimize the impact of chucked wafer non-flat topography. However, to maintain high throughput and improve critical dimension uniformity (CDU) at sub-wavelength line-widths requires continuous improvement in the incoming silicon wafer flatness. In this paper we report extensive experimental results that review existing wafer flatness metrics and propose the addition of a new metric. The new metric emulates the scanning motion of exposure by integrating the defocus that each point on the wafer experiences during exposure. We show that this method is in better spatial agreement with measured defocus in step-and-scan exposure tools. Simple metrics of moving average (MA) defocus prediction analysis will be defined and shown to correlate very well to post exposure defocus data. These experiments were enabled by the creation of special 300-nm wafers by MEMC. These special wafers include sites with a wide variation in flatness. Prior to exposure the wafers were measured with a high-resolution optical flatness metrology tool (WaferSight by ADE) to obtain industry standard thickness variation (flatness) data. Incoming wafer flatness data is used to predict wafer suitability for lithography at the desired device geometry node (e.g., 90 nm). The flatness data was processed and characterized using both standard metrics (SFQR) and the new MA analysis. The relationship between the industry standard metric (SFQR) and similar metrics applied to MA analysis will be presented. Full two-dimensional maps are used to present spatial correlations and permit simple physical insights into the flatness data sets. Measurements of chucked wafer flatness were made on the same wafers using ASML TWINSCAN in-line metrology. These measurements correlate very well to thickness-based flatness. Un-chucked wafer flatness metrics (SFQR and MA) are shown to correlate well to post exposure defocus data when an appropriate site size is used. This result is discussed in relationship to the industry-accepted practice of specifying un-chucked wafer flatness. Lithography performance tests were made to prove the relevance of the different flatness metrics. The same special wafers are used for lithography performance tests. These tests achieve excellent correlation between post-exposure full-wafer focus control results and predictions based on both SFQ (industry standard) and MA re-mapping of the flatness data. The relationship between measured critical dimension (CD) and defocus is also explored. Point-by-point analysis of CD residual versus measured defocus data nicely follows a Bossung curve. We also show that residual CD values predicted from defocus correlate well with measured values. These experiments confirm the application of industry standard wafer flatness measurements to step-and-scan lithography when appropriately using current metrics. They also present the potential for improved metrics based on the MA defocus prediction analysis to help drive continuous improvement of wafer flatness for advanced step-and-scan lithography.

Determining local residual stresses from high resolution wafer geometry measurements

Multiple thin film deposition steps are central to most semiconductor device fabrication processes. The residual stresses in these thin films can induce both in-plane and out-of-plane distortions to the wafer. These residual stresses can vary spatially across the wafer, and the residual stress distributions can change between lithography steps. This can result in noncorrectable overlay errors in the lithography processes. In order to develop strategies for minimizing overlay errors due to residual stress-induced distortion, there is a critical need for techniques that allow the distributions of residual stresses in deposited thin films to be characterized with high spatial resolution. In this paper, the application of established analytical methods for extracting local residual stress from wafer geometry measurements (shape) is investigated. Three-dimensional finite-element models were used to generate simulated wafer shapes resulting from nonuniform residual stress distributions in thin-films. The results of these finite element simulations were used to assess the effectiveness of established analytical techniques. Furthermore, the results demonstrated that local mean curvature of the wafer shape is a simple metric that can be used to qualitatively describe local residual stress variation across the wafer. The simulations also demonstrated that when residual stresses varied over scales of tens of millimeters that high spatial resolution (<1 mm) shape measurements were required in order to accurately predict local residual stress.

Improvement of depth of focus control using wafer geometry

For several decades, the semiconductor industry has been controlling site flatness of the starting wafer material by defining tight specs on industry-standard site flatness metrics such as SFQR (Site Frontsurface-referenced least sQuares/Range) and ESFQR (Edge Site Frontsurface-referenced least sQuares/Range) that scale with technology nodes. The need for controlling site flatness of the starting material stems from previous research that shows that site flatness directly impacts lithography defocus. The wafer flatness variation changes significantly due to wafer processing downstream such as CMP, etch, and film deposition. Hence, for 2X nm and smaller technology nodes with very stringent focus process windows, it is critical to control wafer flatness variations at critical steps along the semiconductor process flow. In this paper, the capability of an interferometer-based patterned wafer metrology tool to predict lithography defocus is validated by comparison to scanner leveling data. The patterned wafer metrology tool is used to characterize the impact of near-edge flatness changes on the critical dimension (CD) of the contact holes due to different edge CMP process conditions. The results of the characterization illustrate how a site flatness specification or threshold can be developed for critical patterning steps. The paper also illustrates how the patterned wafer metrology tool can be used to identify processes causing site flatness variations. Finally, the site flatness variation at these processes can be monitored using the pattern wafer metrology tool to detect process drifts and excursion before patterning.

Role of wafer geometry in wafer chucking

Abstract. Wafer chucks are used in advanced lithography systems to hold and flatten wafers during exposure. To minimize defocus and overlay errors, it is important that the chuck provide sufficient pressure to completely chuck the wafer and remove flatness variations across a broad range of spatial wavelengths. Analytical and finite element models of the clamping process are presented here to understand the range of wafer geometry features that can be fully chucked with different clamping pressures. The analytical model provides a simple relationship to determine the maximum feature amplitude that can be chucked as a function of spatial wavelength and chucking pressure. Three-dimensional finite element simulations are used to examine the chucking of wafers with various geometries, including cases with simulated and measured shapes. The analytical and finite element results both demonstrate that geometry variations with short spatial wavelengths (e.g., high-frequency wafer shape features) present the greatest challenge to achieving complete chucking. The models and results presented here can be used to provide guidance on wafer geometry and chuck designs for advanced exposure tools.

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

Controlling overlay errors resulting from wafer processing, such as film deposition, is essential for meeting overlay budgets in future generations of devices. Out-of-plane distortions induced on the wafer due to processing are often monitored through high-resolution wafer geometry measurements. While such wafer geometry measurements provide information about the wafer distortion, mechanics models are required to connect such measurements to overlay errors, which result from in-plane distortions. The aim of this paper is to establish fundamental connections between the out-ofplane distortions that are characterized in wafer geometry measurements and the in-plane distortions on the wafer surface that lead to overlay errors. First, an analytical mechanics model is presented to provide insight into the connection between changes in wafer geometry and overlay. The analytical model demonstrates that the local slope of the change in wafer shape induced by the deposition of a residually stressed film is related to the induced overlay for simple geometries. Finite element modeling is then used to consider realistic wafer geometries and assess correlations between the local slope of the wafer shape change induced by the deposition of a stressed film and overlay. As established previously, overlay errors only result when the stresses in the film are non-uniform, thus the finite element study considers wafers with several different nonuniform residual stress distributions. Correlation between overlay and a metric based on a corrected wafer slope map is examined. The results of the modeling and simulations are discussed and compared to recently published experimental results.

Simulation of non-uniform wafer geometry and thin film residual stress on overlay errors

The deposition of residually stressed films in semiconductor manufacturing processes introduces elastic distortions in the wafer that can contribute to overlay errors in lithographic patterning. The distortion induced by film deposition causes out-of-plane distortion (i.e. wafer shape) that can be measured with commercial metrology tools as well as in-plane distortion that leads to overlay errors. In the present work, overlay errors and out-of-plane distortion of wafers resulting from residual stresses that are non-uniform over the area of wafer are examined using computational mechanics modeling. The results of these simulations are used to examine the correlations between wafer shape features and overlay errors. Specifically, connections between overlay errors and metrics based on the slope of the wafer shape are assessed.