Howard R. Huff

Gate stack technology for nanoscale devices

The historical evolution of gate stack technology for silicon devices is reviewed to provide insight on the challenges in this technology for scaled nanoscale CMOS devices and non-Si-based devices.

Dielectrics for future transistors

Abstract Responding to the market growth for computational power in various applications, semiconductor technology continues unabated in its drive towards higher transistor densities and faster transistors. The general direction of this trend is scaling down the critical transistor dimensions of integrated circuit (IC) components.

Interfacial Layer-Induced Mobility Degradation in High-

Analysis of electrical and scanning transmission electron microscopy (STEM) and electron energy loss spectra (EELS) data suggests that Hf-based high-k dielectrics deposited on a SiO2 layer modifies the oxygen content of the latter resulting in reduction of the oxide energy band gap and correspondingly increasing its k value. High-k deposition on thinner SiO2 films, below 1.1 nm, may lead to the formation of a highly oxygen deficient amorphous interfacial layer adjacent to the Si substrate. This layer was identified as an important factor contributing to mobility degradation in high-k transistors.

k

High-k dielectric materials including zirconium oxide and hafnium oxide produced by atomic layer deposition have been evaluated for thermal stability. As-deposited samples have been compared with rapid thermal annealed samples over a range of source/drain dopant activation temperatures consistent with conventional complimentary metal oxide semiconductor polysilicon gate processes. Results of this initial investigation are presented utilizing analyses derived from X-ray diffraction (XRD), X-ray reflectometry (XRR), medium energy ion spectroscopy, high resolution transmission electron microscopy (HRTEM), tunneling atomic force microscopy, scanning electron microscopy, Auger electron spectroscopy and secondary ion mass spectroscopy. Changes in interface and surface roughness, percent crystallinity and phase identification for each material as a function of anneal temperature have been determined by XRD, XRR and HRTEM. Finally, high-k wet etch issues are presented relative to subsequent titanium silicide blanket film resistivity values.

Transistors

The gate stack should be regarded as a multi-element interfacial layered structure wherein the high-k gate dielectric and gate electrodes (and their corresponding interfaces) must be successfully comprehended. The surface clean and subsequent surface conditioning prior to high-k deposition as well as post-deposition annealing parameters significantly impact the equivalent oxide thickness and leakage current as well as the traditional parameters such as threshold voltage, saturation current, transconductance, and sub-threshold swing. The control of both the fixed electrical charges and charge traps incorporated at the various interfaces and within the high-k bulk film is of paramount importance to achieve the requisite transistor characteristics and, in particular, the effective carrier mobility. Interactive effects within the gate stack process modules and the subsequent integrated circuit fabrication process require the utmost attention to achieve the desired IC performance characteristics and help facilitate the continuance of Moores Law towards the 10-nm physical gate length regime.

Experimental observations of the thermal stability of high-k gate dielectric materials on silicon

Fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V/sub th/ instability, low DC mobility and poor reliability. The intrinsic characteristics of high-k transistors free from FTCE are demonstrated using ultra-short pulsed I-V measurements, and it is found that the intrinsic mobility of high-k devices can be much higher than what has been observed in DC based measurements. The FTCE model suggests that many of DC characterization methods developed for SiO/sub 2/ devices are not sufficiently adequate for high-k devices that exhibit significant transient charging. The existence of very strong concurrent transient charging during various reliability tests also degrades the validity of test results. Finally, the implication of FTCE on the high-k implementation strategy is discussed.

High-k gate stacks for planar, scaled CMOS integrated circuits

Changes in the composition of atomic layer deposited, uncapped hafnium dioxide films, as a function of anneal temperature, have been evaluated by several advanced analytical techniques including; x-ray reflectivity, high-resolution transmission electron microscopy, and medium energy ion scattering. It is shown that such measurements of the high-k/Si interface layer are inconclusive and may be misinterpreted to suggest the presence of an HfxSi1−xO2 (x∼0.5) transition layer. It is also demonstrated that high-temperature anneal of uncapped films may result in the formation of voids which propagate through the dielectric layer into the silicon substrate. Trends associated with defect generation, interfacial oxide growth, and the low probability of material intermixing during anneal processing are discussed.

Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)

Reduced metal contamination levels become ever more critical as ultralarge scale integrated device feature sizes shrink to ≤0.25 μm. Wafers may be contaminated with metals during their manufacture, but metals are more likely to be introduced at the wafer surface during integrated circuit processing. During high-temperature processing steps, the surface contaminants diffuse rapidly into the wafer bulk. Because carrier lifetime and diffusion length are strongly affected by the presence of parts per trillion levels of electrically active metal-related defect centers in the bulk of the wafer, these properties can be used to detect the presence of metal contamination. Unfortunately, these techniques are sometimes misused and misinterpreted. The more common techniques, their benefits, and limitations on their interpretation are discussed. A unified taxonomy to describe carrier lifetime characteristics is also proposed.

Physicochemical properties of HfO2 in response to rapid thermal anneal

Distinguishing false counts caused by surface microroughness and haze when measuring particles below 0.1 μm has become a significant concern for ultralarge scale integrated (ULSI) product yield. Initial results are presented from an industry-wide, cross-functional, SEMATECH task force exploring this issue by investigating both measurement capability and alternative detector strategies for laser surface scanners. Polystyrene latex (PSL) spheres and real-world particles deposited under controlled conditions on 150 mm polished silicon wafers are used. Particle counting measurements taken at several facilities using the same model of laser surface scanner and the same instrument parameter settings are compared. Silicon particles are consistently sized incorrectly when the laser surface scanner is calibrated using standardized procedures utilizing PSL spheres. Measurements from similarly prepared samples using angle-resolved scattering (ARS) to obtain scattering cross section as a function of angle are favorably compared to a numerical light scattering model. Modeling allows the comparison of data from instruments which measure ARS from individual particles as well as those which measure ARS from multiple identical particles. The improved signal-to-noise ratio of the multiple particle technique allows study of particle scattering at sizes below typical commercial equipment detection limits. A novel haze surface is described which can be used to verify the modeling of both research and commercial light scattering instruments.

Interpretation of Carrier Recombination Lifetime and Diffusion Length Measurements in Silicon

Abstract A bond-breaking phenomenon responsible for oxide degradation during electrical stress is considered as a multi-step process that includes generation of precursor breakdown defects by the injected electrons directly in the bulk oxide and the subsequent breakdown of the defects bonds. Precursor defect generation is attributed to the capture/scattering of the injected electrons by the localized gap states associated with oxide structural imperfections. These precursor defects, represented by significantly elongated Si–O bonds or Si–Si bonds are shown to be unstable due to their vibrational excitation and polarization induced by temperature and an applied electric field, respectively; breakdown of the weak precursor defects bonds results in the formation of the E ′ centers. The proposed model suggests that new precursor defects are preferentially created in the vicinity of the previously generated E ′ centers. This leads to the formation of defect clusters, which can grow and coalesce throughout the oxide, contributing to oxide leakage current and eventual oxide breakdown. The model describes the charge-to-breakdown dependence on the electron fluence and energy, electric field, temperature and oxide thickness.