Tatsuya Ezaki

HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation

The compact MOSFET model development trend leads to models based on the channel surface potential, allowing higher accuracy and a reduced number of model parameters. Among these, the Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) solves the surface potentials with an efficient physically correct iteration procedure, thus avoiding additional approximations without any computer run-time penalty. It is further demonstrated that excellent model accuracy for higher-order phenomena, which is a prerequisite for accurate RF circuit simulation, is achieved by HiSIM without any new model parameters in addition to those for describing the current-voltage characteristics

Completely Surface-Potential-Based Compact Model of the Fully Depleted SOI-MOSFET Including Short-Channel Effects

The reported circuit simulation model Hiroshima University semiconductor technology academic research center IGFET model silicon-on-insulator (HiSIM-SOI) for the fully depleted SOI-MOSFET is based on a complete surface-potential description. Not only the surface potential in the MOSFET channel, but also the potentials at both surfaces of the buried oxide are solved iteratively, which allows including of all relevant device features of the SOI-MOSFET explicitly and in a physically correct way. In particular, an additional parasitic electric field, induced by the surface-potential distribution at the buried oxide, has to be included for accurate modeling of the short-channel effects. The total iteration time for surface potential calculation with HiSIM-SOI is under most bias conditions only a factor 2.0 (up to a factor 3.0 for some bias conditions) longer than for the bulk-MOSFET HiSIM model, where just the channel surface potential is involved. It is verified that HiSIM-SOI reproduces measured current-voltage (I-V) and 1/f noise characteristics of a 250-nm fully depleted SOI technology in the complete operating range with an average error of 1% and 15%, respectively. Stable convergence of HiSIM-SOI in the circuit simulation is confirmed

The physics and modeling of MOSFETS : surface-potential model HiSIM

Semiconductor Device Physics Basic Compact Surface-Potential Model of the MOSFET Advanced MOSFET Phenomena Modeling Capacitances Noise Models Non-Quasi-Static (NQS) Model Leakage Currents Source/Bulk and Drain/Bulk Diode Models Source/Drain Resistances Effects of the Source/Drain Diffusion Length for Shallow Trench Isolation (STI) Technologies Summary of Model Equations Exclusion of Modeled Effects and Model Flags.

A Carrier-Transit-Delay-Based Nonquasi-Static MOSFET Model for Circuit Simulation and Its Application to Harmonic Distortion Analysis

In this paper, a compact model of nonquasi-static (NQS) carrier-transport effects in MOSFETs is reported, which takes into account the carrier-response delay to form the channel. The NQS model, as implemented in the surface-potential-based MOSFET Hiroshima University STARC IGFET model, is verified to predict the correct transient terminal currents and to achieve a stable circuit simulation. Simulation results show that the NQS model can even reduce the circuit simulation time in some cases due to the elimination of unphysical overshoot peaks normally calculated by a QS-model. An average additional computational cost of only 3% is demonstrated for common test circuits. Furthermore, harmonic distortion characteristics are investigated using the developed NQS model. While the distortion characteristics at low drain bias and low switching frequency are determined mainly by carrier mobility, distortion characteristics at high frequency are found to be strongly influenced by channel charging/discharging

Effects of Selecting Channel Direction in Improving Performance of Sub-100 nm MOSFETs Fabricated on (110) Surface Si Substrate

We investigated the low field mobility and short channel characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) on (110) surface Si substrates with various channel directions from the viewpoints of experiment and numerical simulation. We found that the mobility (µ) ratio of (110) substrates to (001) substrates (µ(110)/µ(001)) does not depend on the vertical electric field due to the identical surface roughness for (110) and (001) substrates. We verified mobility enhancement and its channel direction dependence by conducting a detailed carrier transport simulation using a full band model and relaxation time approximation. We obtained good threshold voltage (Vth) lowering characteristics due to the suppression of channeling at the source and drain (SD) extension by implant sequence control. Our results showed that the improvement in propagation delay time (CV/I) and on-current ratio of nMOS to pMOS (Ionn/Ionp) obtained by using an optimized combination of channel directions and a (110) surface Si substrate is attractive for future LSIs down to the sub-100 nm region.

R-matrix theory of quantum transport and recursive propagation method for device simulations

We present a theory of quantum transport based on spectral expansion of Green’s function in an open system. In continuous models, this representation makes it possible to avoid discretization of the device area and achieve a much higher numerical accuracy with a lower computational burden compared to common grid schemes. We formulate a numerical method which enables all the observables of interest to be propagated through the device area so that the major portion of the computation time scales linearly with the device volume. As an illustration, we apply the method to quantum ballistic electron transport in model three-dimensional metal oxide semiconductor field effect transistors.

Analysis and Compact Modeling of MOSFET High-Frequency Noise

We have developed a high-frequency noise model for short channel MOSFETs by considering the position dependent surface potential which results in a non-uniform mobility distribution along the channel. The chosen approach successfully reproduces the induced-gate noise and the cross-correlation noise between drain and gate for short channel MOSFETs without additional model parameters. In particular, the gate noise characteristics at GHz frequencies are accurately captured. The newly developed high-frequency noise model is implemented in the complete surface-potential based MOSFET model HiSIM (Hiroshima-university STARC IGFET Model) for circuit simulation

HiSIM2 Circuit simulation - Solving the speed versus accuracy crisis

The development trend in compact modeling goes toward surface-potential-based approaches and leads to models like HiSIM2, with higher accuracy, fewer model parameters, and shorter computer runtime than achievable with the conventional threshold-voltage-based approaches. The main motivation for continuing this development effort is to realize a sufficient design capability of RF circuits with advanced MOSFETs, where many higher-order phenomena affect the circuit performance, as well as of large mixed-signal circuits, where both accuracy and short simulation time are a must. The trend toward the surface potential brings compact modeling for circuit simulation also much closer to 2D and three-dimensional numerical device simulation. Therefore, both approaches can now come together and work united to achieve the common goal of realizing rapid technology progress for the benefit of the society

Impact of floating dot distribution on memory characteristics of self-aligned dots-on-nanowire memory

A nanowire memory device with self-aligned Si nanoscale floating dots has been fabricated to overcome the tradeoff between retention time and programming speed. The dependence of memory characteristics on the dot number and distribution have been systematically analyzed experimentally and numerically to provide design guidelines for optimizing device performance. Distributing multiple floating dots in series along the channel with each dot covering the whole channel width is essential for better retention characteristics, while maintaining similar programming characteristics without increasing the operating voltage. The spacing between dots is also an important factor for optimizing device performance. Taking into account the compatibility of the fabrication process with that of the conventional flash-type nonvolatile memory, the self-aligned dots-on-nanowire memory with multiple floating dots distributed in series along a nanowire channel is the best structure for high-performance memory.

Solution of the Poisson Equation with Coulomb Singularities

We present a new method of calculating electrostatic potential in electronic devices of complicated geometry with singular charge distribution. The method is based on analytical representation of regular and singular parts of the potential function which can be constructed independently in different parts the device. Parameters of such representation are calculated recursively and large scale N3 computer operations are avoided. The method is robust, fast, does not have limitations on the device geometry and can be readily used in statistical simulations. We illustrate the method by computing the electrostatic potential in double-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with a positive impurity in the intrinsic channel.