Ryosuke Inagaki
Waseda University
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Publication
Featured researches published by Ryosuke Inagaki.
IEEE Transactions on Electron Devices | 2006
Mitiko Miura-Mattausch; Norio Sadachika; Dondee Navarro; G. Suzuki; Youichi Takeda; Masataka Miyake; Tomoyuki Warabino; Yoshio Mizukane; Ryosuke Inagaki; Tatsuya Ezaki; Hans Jürgen Mattausch; Tatsuya Ohguro; Takahiro Iizuka; Masahiko Taguchi; Shigetaka Kumashiro; S. Miyamoto
The compact MOSFET model development trend leads to models based on the channel surface potential, allowing higher accuracy and a reduced number of model parameters. Among these, the Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) solves the surface potentials with an efficient physically correct iteration procedure, thus avoiding additional approximations without any computer run-time penalty. It is further demonstrated that excellent model accuracy for higher-order phenomena, which is a prerequisite for accurate RF circuit simulation, is achieved by HiSIM without any new model parameters in addition to those for describing the current-voltage characteristics
Ipsj Transactions on System Lsi Design Methodology | 2009
Ryosuke Inagaki; Norio Sadachika; Dondee Navarro; Mitiko Miura-Mattausch; Yasuaki Inoue
A GIDL (Gate Induced Drain Leakage) current model for advanced MOSFETs is proposed and implemented into HiSIM2, complete surface potential based MOSFET model. The model considers two tunneling mechanisms, the band-to-band tunneling and the trap assisted tunneling. Totally 7 model parameters are introduced. Simulation results of NFETs and PFETs reproduce measurements for any device size without binning of model parameters. The influence of the GIDL current is investigated with circuits, which are sensitive to the change of the stored charge due to the GIDL current.
topical meeting on silicon monolithic integrated circuits in rf systems | 2006
K. Machida; Dondee Navarro; Masataka Miyake; Ryosuke Inagaki; Norio Sadachika; Tatsuya Ezaki; Hans Jürgen Mattausch; Mitiko Miura-Mattausch
A consistent non-quasi-static MOSFET model for time-domain and frequency-domain circuit simulation is developed. The model takes into account the time delay for carriers to form the channel, which is neglected in conventional quasi-static models. The model, as implemented into the surface-potential-based MOSFET model HiSIM, is verified to calculate correct Y-parameters in the frequency domain. The computational runtime cost of the model is comparable to a conventional quasi-static modeling approach
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 2005
Atsushi Kurokawa; Masanori Hashimoto; Akira Kasebe; Zhangcai Huang; Yun Yang; Yasuaki Inoue; Ryosuke Inagaki; Hiroo Masuda
Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2--10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.
international conference on communications, circuits and systems | 2007
Ryosuke Inagaki; Mitiko Miura-Mattausch; Yasuaki Inoue
A GIDL (Gate Induced Drain Leakage) current model for advanced MOSFETs has been proposed and implemented into HiSIM2, first complete surface potential based model. The model consists of one tunneling mechanism considering two tunneling currents, band to band tunneling (BTBT) and trap assisted tunneling (TAT), and requires totally 7 model parameters covering all bias conditions. Simulation results of NFETs and PFETs reproduce measurements for any device size without binning. Validity of the model has been tested with a circuit, which is sensitive to the change of the stored charge due to tunneling current.
international conference mixed design of integrated circuits and systems | 2007
Y. Furui; M. Miura-Mattausch; Norio Sadachika; Masataka Miyake; Tatsuya Ezaki; Hans Jürgen Mattausch; Tatsuya Ohguro; Takahiro Iizuka; Ryosuke Inagaki; N. Fudanuki
STARC (Semiconductor Technology Academic Research Center) is a research consortium co-founded by major Japanese semiconductor companies, whose mission is to contribute to the growth of the Japanese semiconductor industry by developing leading-edge SoC design technologies. One of the achievements enabled by the academia collaboration is HiSIM (Hiroshima University STARC IGFET Model) an advanced MOSFET Model. The HiSIM2 version includes required features in modeling for the 45 nm technology node and beyond such as the STI effect. A major development is an improved model consistency, which enables even modeling of the technology variation accurately. HiSIM2 realizes both accurate and fast circuit simulation.
Ieej Transactions on Electrical and Electronic Engineering | 2008
Ryosuke Inagaki; Norio Sadachika; Dondee Navarro; Mitiko Miura-Mattausch; Yasuaki Inoue
Ieej Transactions on Electrical and Electronic Engineering | 2010
Ryosuke Inagaki; Norio Sadachika; Dondee Navarro; Mitiko Miura-Mattausch; Yasuaki Inoue
情報処理学会論文誌 論文誌トランザクション | 2009
Ryosuke Inagaki; Norio Sadachika; Dondee Navarro
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 2009
Ryosuke Inagaki; Norio Sadachika; Mitiko Miura-Mattausch; Yasuaki Inoue