Oleg Garitselov

A Comparative Study of Metamodels for Fast and Accurate Simulation of Nano-CMOS Circuits

Fast simulation is a bottleneck for design space exploration of complex nanoscale CMOS (nano-CMOS) analog and mixed-signal (AMS) circuits. This paper presents the use of “metamodels” for fast and accurate AMS circuit design exploration. A design process flow that uses metamodels is introduced. Metamodel generation is the most time-consuming step of the design flow. Consequently, accurate and fast sampling of the design space is essential for the creation of the metamodel. Different sampling techniques are investigated to minimize the number of samples required. This paper uses two nanoscale CMOS analog circuits: a 45-nm ring oscillator and a 180-nm LC-VCO, as case studies. It is observed that the parasitics generated from the physical design of the circuits have a drastic effect on their performance metrics, such as frequency. Four alternative sampling techniques, both random [Monte Carlo (MC)] and uniform [Latin hypercube sampling (LHS), middle Latin hypercube sampling (MLHS), and design of experiments (DOEs)], are considered and compared for speed and accuracy. This paper provides a thorough exploration of these sampling techniques to determine which one is more suitable to minimize sampling size for metamodel generation and optimize the design cycle. Experiments show that LHS sampling is best for both circuits, followed by MLHS, MC, and DOE. In this paper, it is also shown that polynomial metamodels of order higher than two (which are commonly used) provide best accuracy.

Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling

Design optimization methodologies for AMS-SoCs with analog, digital, and mixed-signal portions have not received significant attention, due to their high complexity. In mixed-signal circuit design, optimization and simulation are still important issues as they make the design cycle longer. This paper presents a new approach to reduce design optimization time. The approach relies on the fact that optimization carried out over a metamodel (which is an abstracted representation of the circuit model) instead of the actual circuit will allow fast design space exploration and reduce the design cycle time. In this paper three different optimization algorithms are compared: exhaustive search, tabu search and simulated annealing algorithms are analyzed to determine their suitability for metamodeling-based optimization. A ring oscillator is designed for a 45 nm nano-CMOS technology and the post-layout parasitic netlist is used as a test case for a comparative study. It is observed that the metamodel-based simulated-annealing optimization algorithm achieved ∼9000× speed-up over the actual circuit-based optimization.

Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study

Fast design space exploration of complex nano-CMOS mixed-signal circuits is an important problem. In this paper, a design process flow that uses metamodels is introduced. In this flow the most important task is the sampling of the design space. In this paper, different sampling techniques for producing an accurate metamodel are investigated to minimize the number of samples required by using a nano-CMOS ring oscillator (RO) as an example. Through SPICE simulations, it is shown that the parasitics have a drastic effect on performance metrics, such as the frequency of oscillation. Alternative sampling techniques, both random, such as Monte Carlo (MC), and uniform, such as Latin Hypercube Sampling (LHS), and Design of Experiments (DOE), are considered as and compared for speed and accuracy. Due to the time constraints of the circuit design process, this paper can be used as a guideline for which sampling technique will produce the most accurate result to minimize the design time. All a experimental results are presented for a 45 nm technology.

Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization

At the nanoscale domain, the simulation, design, and optimization time of the circuits have increased significantly due to high-integration density, increasing technology constraints, and complex device models. This necessitates fast design space exploration techniques to meet the shorter time to market driven by consumer electronics. This paper presents non-polynomial metamodels (surrogate models) using neural networks to reduce the design optimization time of complex nano-CMOS circuit with no sacrifice on accuracy. The physical design aware neural networks are trained and used as metamodels to predict frequency, locking time, and power of a PLL circuit. Different architectures for neural networks are compared with traditional polynomial functions that have been generated for the same circuit characteristics. Thorough experimental results show that only 100 sample points are sufficient for neural networks to predict the output of circuits with 21 design parameters within 3% accuracy, which improves the accuracy by 56% over polynomial metamodels. The generated metamodels are used to perform optimization of the PLL using a bee colony algorithm. It is observed that the non-polynomial (using neural networks) metamodels achieve more accurate results than polynomial metamodels in shorter optimization time.

Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLL

An automated top-down design flow to achieve physical design of Analog/Mixed-Signal Systems-on-Chip (AMS-SoCs) is difficult, especially for nano-CMOS. Process variation effects have profound impact on the performance of silicon versus layout design. In this paper metamodels, (surrogate models) and Particle Swarm Optimization (PSO) have been combined in an automated physical design flow for fast design exploration of AMS-SoCs. Neural network based non-polynomial metamodels that handle large numbers of design parameters, are used to predict the statistical process variation effects instead of exhaustive Monte Carlo simulations. The PSO algorithm is used for optimization of the AMS-SoC components using their metamodels instead of the actual circuit. The PSO algorithm followed a two step approach: local and global. The physical design of a Phase Locked Loop (PLL) is considered as a case study circuit. The proposed design flow is approximately 5 times faster while the error is under 2% compared to the Monte Carlo analysis.

Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design

The drive for ultra efficient and low-cost portable devices continues to push the need for low power circuit designs. The increasing transistor density and complexity of IC designs aggravates the task of producing efficient low power and low cost design. The short time to market (TTM) also increases this burden on designers, as optimal designs have to be produced in an ever decreasing amount of time. This paper presents an optimization design flow methodology that optimizes the power (accounting leakage) consumption of integrated circuits (ICs). The design flow incorporates a stochastic gradient descent (SGD) based algorithm and is implemented using a 45 nm thermal sensor circuit as case study. Power-efficient high-sensitive thermal sensors are important to reduce the burden on the systems or circuits that they are implanted to sense. Experiments are performed to apply the proposed design flow methodology on the thermal sensor with the power consumption as the design objective while keeping the temperature resolution as a constraint. Experiments on full-blown (RCLK) netlist of sense amplifier show a reduction in power consumption by 38%.

Parabilis: Speeding up Single-Threaded Applications by Extracting Fine-Grained Threads for Multi-core Execution

The trend in architectural designs has been towards using simple cores for building multicore chips, instead of a single complex out-of-order (OOO) core, due to the increased complexity and energy requirements of out of order processors. Multicore chips provide better performance when compared with OOO cores while executing parallel applications. However, they are not able to exploit the parallelism inherent in single threaded applications. To this end, this paper presents a compiler optimization methodology coupled with minimal hardware extensions to extract simple fine-grained threads from a single-threaded application, for execution on multiple cores of a chip multiprocessor (CMP). These fine-grained threads are independent and eliminate the need for communication between cores, reducing costly communication latencies. This approach, which we call Parabilis is scalable for up to eight cores, and does not require complex hardware additions to simple multicore systems. Our evaluation shows that Parabilis yields an average speedup of 1.51 on an 8-core CMP architecture.

Metamodel-assisted ultra-fast memetic optimization of a PLL for WiMax and MMDS applications

With CMOS technologies progressing deeper into the nano-scale domain the design of analog and mixed-signal components is becoming very challenging. The presence of parasitics and the complexity of calculations involved create an enormous challenge for designers to keep their design within specifications when reaching the physical layout stage of the design process. This paper proposes a novel ultra-fast design flow that uses memetic-based optimization algorithms over neural-network based non-polynomial metamodels for design-space exploration. A new heuristic optimization algorithm which is based on memetic algorithms and artificial bee colony optimization is introduced. The design flow relies on a multiple-layer feedforward neural network metamodel of the nano-CMOS circuit. Using a CMOS PLL circuit it is shown that the proposed design flow is flexible and robust while it achieves optimal design to two different wireless specifications, WiMax and MMDS. Experimental results show that the proposed approach is 2.4 × faster than the swarm based optimization over the same metamodels.

Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration

Current Verilog-AMS system level modeling does not capture the physical design (layout) information of the target design as it is meant to be fast behavioral simulation only. Thus, the results of behavioral simulation can be very inaccurate. In this paper a paradigm shift of the current trend is presented that integrates layout level information (with full parasitics) in Verilog-AMS through polynomial metamodels such that system-level simulation of a mixed-signal circuit/system is realistic and as accurate as the true parasitic netlist simulation. As a specific case study, a voltage-controlled oscillator (VCO) Verilog-AMS behavioral model and design flow are proposed to assist fast PLL design exploration. Based on a quadratic polynomial metamodel, the PLL simulation achieves approximately a 10X speedup compared to the layout extracted, parasitic netlist. The simulations using this behavioral model attain high accuracy. The observed error for the simulated lock time and average power consumption are 0.7% and 3%, respectively. This behavioral metamodel approach bridges the gap between layout accurate but fast simulation and design space exploration.