Olof Tornblad

High frequency power LDMOS technologies for base station applications status, potential, and benchmarking

LDMOS technologies based in G. Ma et al. (1996) and H. Brech et al. (2003) have been in dominate position in wireless base station applications for frequencies ranging from 450MHz to 2.7GHz for the last 10 years due to performance, cost, reliability, and power capability advantages. This paper reviews the leading edge LDMOS development at Infineon and discusses future potential and limitation for LDMOS technologies in general; benchmarking with alternative technologies is also presented

Modeling and Measurements of Electrical and Thermal Memory Effects for RF power LDMOS

Accurate modeling of memory effects is important for design of amplifiers with high requirements on linearity. In this work, asymmetries in third order intermodulation distortion products (IM3) were measured for different tone-spacings and compared to simulations. An accurate large-signal model and careful modeling of the test circuit, especially the drain bias feeds is important for correct prediction of sideband asymmetries. Transient thermal measurements were employed to extract a thermal network with two time constants, one for the die and another one for the package. The IM3 asymmetries were found to be dominated by impedances in the output circuit for large tone-spacings; for very small tone-spacings (< 10 kHz), thermal effects have an important influence. The IM3 asymmetries agreed qualitatively well between simulations and measurements as a function of output power for different tone-spacings.

Linearity Analysis of RF LDMOS Devices Utilizing Harmonic Balance Device Simulation

Linearity is one of the most important characteristics for current and next-generation RF power devices for wireless communication. In this work, linearity of power LDMOS devices is analysed by using a unique harmonic balance device simulator. Sweet-spots in the third order intermodulation distortion product (IM3) are explained and found to be in agreement with measurements and compact modeling. For demonstration of the simulation methodology, a change in the lightly doped drain (LDD) region doping concentration was performed and the effect on linearity was analysed.

Linearity Analysis of Lateral Channel Doping in RF Power MOSFETs

Advanced harmonic balance simulation capabilities have been used to investigate linearity behavior in RF power laterally diffused metal-oxide semiconductor (LDMOS) devices with different laterally graded channel doping profiles. Harmonic balance analysis provides relevant device information from device-level simulations and yields performance metrics of RF circuits. The linearity behavior of simple quasi-1-D structures with different graded channel doping profiles was investigated; the analysis was then extended to a more realistic power LDMOS device. The third-order intermodulation distortion product reveals the important role of lateral channel doping. The analysis lays groundwork for device optimization for improved linearity.

Device Analysis of Linearity in RF Power Devices by Harmonic Balance Device Simulation

Low distortion is one of the most important concerns for current and next-generation wireless communication systems. In this work, the linearity of RF power MOS devices are analysed by using a unique harmonic balance device simulator. Sweet-spots in the third order intermodulation distortion product (IM3) were investigated and interpreted in terms of bias and device design parameters. The demonstrated methodology helps in laying ground-work for improved device design and investigation of new device concepts for improved linearity

Substrate network modeling of RF Power LDMOS devices including nonlinear effects

Substrate network modeling of RF Power LDMOS devices is important for accurate modeling at higher frequencies. Substrate losses can account for a considerable amount of the losses in the device and directly affects the efficiency, which is one of the most critical performance criteria of a power amplifier. In this paper, an improved substrate network model for RF Power LDMOS devices is presented that can more accurately predict these losses and be of help in designing improved device structures. Nonlinear resistors representing a depleting drain to body junction as a function of drain to source bias are included in a physical way. It is shown that the model gives good agreement with s-parameters for varying LDD lengths and as a function of drain to source bias.

A Study of memory effects of RF power LDMOS before and after digital predistortion

Sideband asymmetries in distortion products are created due to electrical and thermal memory effects and this can be difficult to correct for in a digital predistortion algorithm. In this study, sideband asymmetries in third-order intermodulation distortion products before and after digital predistortion were investigated using 2-tone and 2-carrier WCDMA signals. The parallel Hammerstein (PH) model was used in the digital predistortion algorithm. The sign of the asymmetries before correction were found to depend on power level. Memoryless correction lead to an increase in asymmetries for some power ranges whereas using a PH model of order 13 with only one order of memory length lead to good correction over a large power range.

A New Methodology for Efficient and Reliable Large- Signal Analysis of RF Power Devices

In RF power device design, much of the analysis is based on measurements. Complete analysis by simulation is often avoided because the high-frequency, largesignal operation makes device simulation unsuitable, and the difficulties in obtaining a good physical compact model make circuit simulation inaccurate. This work presents a methodology that overcomes these limitations by utilizing a combination of device and circuit simulations to characterize large-signal operation of RF power devices quickly and accurately. Results show that circuit simulations using an extracted Root model agree well with device simulation for the intrinsic device. It is also demonstrated that changes in device design are reflected in circuit-level RF performance.