P. C. Murley

Soft-error Monte Carlo modeling program, SEMM

The application of a computer program, SEMM (Soft-Error Monte Carlo Modeling), is described. SEMM calculates the soft-error rate (SER) of semiconductor chips due to ionizing radiation. Used primarily to determine whether chip designs meet SER specifications, the program requires detailed layout and process information and circuit Q{sub crit} values.

Accurate, predictive modeling of soft error rate due to cosmic rays and chip alpha radiation

We report here the development of a unique and comprehensive computer program (SEMM) to calculate the probability of soft fails in integrated circuits due to alpha particles emanating from the chip materials and due to terrestrial cosmic rays. This model treats all failure modes on an event by event basis allowing for all nuclear reactions and pulse shape effects. It is a three-dimensional design tool that takes the detailed chip layout and profile information to compute the soft error rate and is used without any parameter fitting. SEMM has been extensively tested with hot sources, high energy proton beams, and high elevation cosmic ray tests. Applications of SEMM to bipolar and CMOS chips and considerations for building in reliability for radiation induced soft fails are also discussed.<<ETX>>

Dynamics of Charge Collection from Alpha-Particle Tracks in Integrated Circuits

We studied the transient characteristics of charge collection from alpha-particle tracks in silicon devices. We have run computer calculations using the finite element method, in parallel with experimental work. When an alpha particle penetrates a pn-junction, the generated carriers drastically distort the junction field. After alpha particle penetration, the field, which was originally limited to the depletion region, extends far down into the bulk silicon along the length of the alpha-particle track and funnels a large number of carriers into the struck junction. After less than one nanosecond, the field recovers to its position in the normal depletion layer, and, if the track is long enough, a residue of carriers is left to be transported by diffusion. The extent of this field funneling is a function of substrate concentration, bias voltage, and the alpha-particle energy.

A statistical approach to the design of diffused junction transistors

Monte Carlo methods of statistical analysis are applied to the problems of transistor design and optimization. The experimental tolerances associated with any diffusion process are shown to represent an important factor in the initial design of diffused junction transistors. Many transistor parameters exhibit a substantial degree of sensitivity to small variations in the diffusion process. This is confirmed by a comparison between the theoretical and experimental open-base breakdown voltage, and current gain, for a large number of devices. It is therefore proposed that the design of a transistor be based upon attaining a specified set of electrical characteristics when the device is assumed to be fabricated by a non-ideal diffusion process. An electronic computer has been used in an investigation of the foregoing problem. The investigation shows further that a margin-of-safety must be designed into each electrical parameter of a transistor to assure that the resulting device satisfies a given set of design specifications, even though this margin-of-safety may differ for each parameter. In this paper examples are presented to illustrate the theoretical trade-off between several opposing transistor parameters that exhibit a substantial degree of variability due to a non-ideal diffusion process.

Base Region Transport Characteristics of a Diffused Transistor

A one‐dimensional analysis is given on the minority carrier transport characteristics of a transistor base region containing an arbitrary drift field distribution. This field is assumed to enhance—or retard—the motion of minority carriers between an emitter and collector junction, thereby modifying the influence of bulk recombination mechanisms. Base region transport efficiency is established in terms of the transistor current gain when an ideal emitter junction is assumed. Applications of this analysis are demonstrated by establishing the base region transport efficiency for diffused transistors. Two types of structures have been analytically investigated: the alloy‐diffused transistor, containing a diffused collector junction and an alloy‐type emitter; and the double‐diffused transistor constructed entirely by diffusion techniques. For practical semiconductor devices, a comparison of these two structures has shown negligible differences in their base region transport efficiency and, furthermore, the dri...

Analysis of epitaxial layer thickness variability in the fabrication of high performance bipolar transistors

Abstract Measurements indicate that a thickness variation of approximately 7·0 per cent (2σ) can be expected from modern epitaxial reactors. This epitaxial layer thickness variability, in conjunction with the technique of designing into a transistor collector junction and buried layer interference, will often produce problems of fabrication reproducibility. Statistical calculations are presented to demonstrate some fabrication difficulties that are mathematically attributable to this thickness variability. Problems arising from simple space-charge layer interference are compared with those arising from deep penetration of the collector junction into its buried layer.

Theoretical current gain of a cylindrical mesa transistor

Abstract For the cylindrical mesa transistor, computation of base-region transport efficiency is considered a boundary-value problem; solution of this problem yields mathematical equations applicable to the design and development of practical semiconductor devices. This analytical method is applied to the problem of minority-carrier transport across a solid-cylinder type structure which approximates the transistor base region. Minority-carrier losses—representing a fundamental limitation upon transistor-current gain—are introduced through an assumption of bulk and surface-recombination mechanisms. Applications of this analysis are illustrated by establishing the common-emitter current gain for typical junction transistors. Assuming, in such computations, physical parameters approximating germanium and silicon diffused devices, the silicon transistor is shown to be less sensitive to surface recombination mechanisms. Further, the existence of an optimum emitter radius is demonstrated for a semiconductor structure similar to the cylindrical hook collector.

Technology CAD at IBM

The IBM suite of TCAD tools for semiconductor process and device modeling is described. The series includes FEDSS for process modeling, FIELDAY for device modeling, FOXi/FIERCE for resistance and capacitance calculation, EXCALIBR and MGP for compact device model generation, and SEMM for soft-error failure probability prediction. Comprising the VATS series of tools, the programs interact through a common database representation, are accessible via a graphics-user-interface WIZARD, and provide for inputs, outputs, and meshing through a number of pre- and post-processor programs.