Pankaj Kumar Pal

High-Performance and Robust SRAM Cell Based on Asymmetric Dual-

This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET) structure using a dual- k spacer. Asymmetric dual-spacer at source shows excellent gate control over the channel due to increase in the outer fringe field at gate/source underlap. Hence, this structure exhibits a superior short-channel effect metric over the conventional/single-spacer underlap FinFET. The proposed asymmetric structure enhances static random access memories (SRAMs) performance in terms of robustness, access times as well as leakage power during the hold, read, and write operations. The hold static noise margin and write margin increases by 5.16% and 5.66%, respectively. The read stability enhances by 13.75% and 19.35% over conventional FinFET SRAM circuit. Furthermore, the leakage power reduces by 60%, and write access time improves by 23.63%. Compared with conventional FinFET-based SRAM, same bit-cell area and read delay are associated with the proposed structure. Supply voltage scalability on SRAM design metrics is also investigated. In addition to SRAM application, underlap length, lateral source/drain doping gradient, and the high- k spacer width are optimized for high-performance digital applications.

k

During recent years, high-k spacer materials have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance that restricts researchers using these devices in high-performance circuits. For the first time, this paper demonstrates the usage of high-k spacer material with an optimized length for effective reduction of circuit delay and an improvement in robustness. An improvised symmetric dual-k spacer (SymD-k) underlap trigate FinFET architecture termed as SymD-k is employed for this purpose. From extensive 3-D simulations, this paper demonstrates that SymD-k device significantly improves overall circuit delay and robustness (noise-margins) with fully capturing the fringe capacitance effects. A CMOS inverter and a three-stage ring-oscillator (RO3) are adopted to carefully investigate the performances. In comparison with the conventional device, the SymD-k device speeds up the RO3 circuit by 27% and 33% using high-k spacer dielectric HfO2 and TiO2, respectively. However, a purely high-k FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effect of underlap length and supply voltage on SymD-k-based RO3 delay over the conventional ones are also dealt in.

Spacer FinFETs

High-k spacer materials have been extensively studied nowadays for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance. Interestingly, this paper demonstrates effective reduction in circuit delay with an optimum usage of high-k spacer material. An asymmetric dual-k spacer trigate (ADS-TG) FinFET architecture is employed for the purpose. From extensive 3-D simulations, it is demonstrated that ADS-TG device significantly improves the overall circuit delay and robustness performance while fully capturing the fringe capacitance effects. A FinFET inverter and a three-stage ring oscillator (RO3) are adopted to investigate the performances carefully. In comparison with the conventional device, the ADS-TG device speeds up the RO3 circuit by 22.6% and 32.4% using high-k spacer dielectrics HfO2 and TiO2, respectively. Contradictorily, a purely high-k FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effects of supply voltage and underlap length on ADS-TG-based RO3 delay over the conventional ones are also dealt in. The ADS-TG device and static RAM based on this device prove to be more variation tolerant in comparison with the conventional configurations.

Investigation of Symmetric Dual-k Spacer Trigate FinFETs From Delay Perspective

Underlap FinFET devices, or trigate transistors, are considered to be the most favorable substitute to the conventional bulk device below 22-nm technology node. However, their application in circuit design requires specific attention because of the fin width quantization and increased parasitic. This paper proposes a double dielectric or dual- k spacers technology to enhance the electrostatic integrity of underlap FinFETs. For the first time, we investigate the circuit performance such as that of static RAMs (SRAMs), based on the proposed dual- k spacer FinFETs. The proposed structure enhances SRAMs performance in terms of robustness, access times, and the leakage power during all possible modes of operation. The hold, read, and write-margin increases by 8.7%, 9.4%, and 10.4%, respectively, as compared with conventional FinFET SRAM. Furthermore, the read and write access times reduces by 56% and 17.1%, respectively. Moreover, the standby leakage power is also reduced by ~ 73% compared with the conventional FinFET-based SRAM while occupying same bit-cell area.

Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis

This paper proposes an overall improvement in performance of Gate-Source/Drain underlap FinFET structure by introducing the concept of dual-k spacer between gate and source. By optimizing the underlap length, we demonstrate the sensitivity of dual-k spacer width. We analyze that the variation in width of high-k presents a noticeable improvements in On-Off current ratio (Ion/Ioff). The proposed structure is verified by TCAD simulations of underlap FinFET device with varying device physical parameters such as spacer width, spacer material etc. and optimizes the width of the high-k and low-k spacer. The proposed device architecture enhances gate control over channel and can be used to design low power digital circuits.

Design Metrics Improvement for SRAMs Using Symmetric Dual-

This paper proposes a dual-k spacer FinFET architecture that shows superior electrostatic integrity over the conventional low-k spacer underlap device and thus suppress SCEs. Furthermore, the proposed dual-k structure explores the possibility of symmetric FinFETs that helps to augment all SRAM design metrics without affecting cell-ratio and pull-up ratio.

k

High permittivity materials have considered as a key enabler in nano-scaled underlap devices to achieve better electrostatic control. However, the enhanced fringing capacitance inherently associated with high-k materials poses several design challenges that limits its usage in high-performance (HP) circuits applications. To simultaneously improve the device and circuit performance, dual-k architecture had been proposed in terms of symmetric and asymmetric architectures. For specific SRAM applications, both the symmetric (SymD-k) and asymmetric (AsymD-kS) architectures performed better than the conventional low-k and purely high-k devices. The performance improvement in AsymD-kS based SRAM cell is due to its asymmetric nature that helps in adjusting the pull-up (PR) and cell-ratio (CR). Contradictorily, the improvements in SymD-k cell are attributed to the enhanced electrostatic integrity that increases SNMs without affecting PR and CR. Therefore, an in-depth comparative analysis between symmetric and asymmetric dual-k spacer architectures are utmost required that helps in understanding their respective electrostatics and its influence on HP circuit/SRAM applications. For the first time, this paper distinguishes the competing effects of symmetric and asymmetric dual-k spacer structures.

Spacer (SymD-

The spin transfer torque (STT) magneto-resistive random access memory (MRAM) often uses bulk and silicon on insulator (SOI) metal oxide semiconductor (NMOS) as access device. However, the drive current reduction due to the substrate bias effect in bulk NMOS and lattice heating effect in silicon on insulator (SOI) NMOS makes them less suitable for STT MRAMs. The reduction in write current actually increases the write errors in STT MRAMs that adversely affects the reliability of STT MRAM cell. Taking these reliability concerns into account, an STT MRAM cell with fully depleted (FD) silicon carbide (4H-SiC) substrate NMOS is presented that is impervious to drive current reduction due to the substrate bias and self heating effects. The proposed STT MRAM cell with FDSIC NMOS exhibits a maximum variation of 3% in the steady state lattice temperature manifesting very low possibility of thermal fatigue and device failures. Moreover, the proposed cell offers extremely low leakage power dissipation that is almost three orders smaller than the conventional cell. The circuit level analysis of STT MRAM is done using calibrated Verilog-A models. Encouragingly, the proposed FDSIC cell demonstrates 45% improvement in write error rate over conventional FDSOI cell.

k

High-ft spacer materials have been extensively researched for the suppression of short-channel effects (SCEs) in nano-scaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance. The dynamic performance with enhanced device electrostatics can be effectively improved by dual-k spacer (SymD-fc) architecture. However, this architecture in sub-20nm node requires special attention towards their performance under process induced variations. For the first time, this paper explores the tolerance of SymD-k architecture and its circuit/SRAM performance under random statistical variations and sensitivity analysis of device parameters. It is observed from the obtained 2D results that the SymD-k device/circuit exhibits least sensitivity to random variations in comparison to the conventional FinFETs.

) FinFETs

In this paper, we present the impact of spacer dielectric on a junctionless transistor (JLT) FinFET based circuit/SRAM memory cell. JLT FinFETs with high-k spacers provide excellent electrostatic integrity as well as reduction in short channel effects (SCEs). Fringing electric field through spacer increases effective channel length in the OFF-state, whereas in ON-state it is unaffected. It is observed that the drive current, leakage current, drain induced barrier lowering (DIBL) and sub-threshold swing (SS) are improved. The JLT structure with spacers leads to better noise-margins of CMOS inverter. Moreover, the JLT architecture also improves the performance of SRAM in terms of static-noise margins (SNMs) and leakage power with increase in high-k spacer value. High-k spacer increase the capacitance of the device, so ring oscillator delay and SRAM access times are degraded.