Paola Favia

The VO2 interface, the metal-insulator transition tunnel junction, and the metal-insulator transition switch On-Off resistance

Transition metal compounds showing a metal-insulator transition (MIT) show complex behavior due to strongly correlated electron effects and offer attractive properties for nano-electronics applications, which cannot be obtained with regular semiconductors. MIT based nano-electronics, however, remains unproven, and MIT devices are poorly understood. We point out and single out one of the major hurdles preventing MIT-electronics: obtaining a high Off resistance and high On-Off resistance ratio in an MIT switch. We show a path toward an MIT switch fulfilling strict Off and On resistance criteria by: (1) Obtaining understanding of the VO2-interface, a protoypical MIT material interface. (2) Introducing a MIT tunnel junction concept to tune switch resistances. In this junction, the metal or insulating phase of the MIT material controls how much current flows through. Adapting the junctions parameters allows tuning the MIT switchs Off and On resistance. (3) Providing proof of principle of the junction and its...

High-mobility Si 1−x Ge x -channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths

This paper is the first to provide a comprehensive study on the layout dependence of scaled Si<inf>1−x</inf>Ge<inf>x</inf>-channel pFETs.

High-k Dielectrics and Metal Gates for Future Generation Memory Devices

The requirements and development of high-k dielectric films for application in storage cells of future generation flash and Dynamic Random Access Memory (DRAM) devices are reviewed. Dielectrics with k-value in the 9-30 range are studied as insulators between charge storage layers and control gates in flash devices. For this application, large band gaps (> 6 eV) and band offsets are required, as well as low trap densities. Materials studied include aluminates and scandates. For DRAM metal-insulator-metal (MIM) capacitors, aggressive scaling of the equivalent oxide thickness (with targets down to 0.3 nm) drives the research towards dielectrics with k-values > 50. Due to the high aspect ratio of MIMCap structures, highly conformal deposition techniques are needed, triggering a substantial effort to develop Atomic Layer Deposition (ALD) processes for the deposition of metal gates and high-k dielectrics. Materials studied include Sr and Ba-based perovskites, with SrTiO3 as one of the most promising candidates, as well as tantalates, titanates and niobates.

Low VT metal-gate/high-k nMOSFETs — PBTI dependence and V T Tune-ability on La/Dy-capping layer locations and Laser annealing conditions

This paper provides a comprehensive study of the abnormal PBTI behaviors recently observed in La/Dy-capped high-k films in low-VT nMOSFETs. We found that process details in thermal budget (or dielectric intermixing) and oxygen content of the metal trigger the onset of these abnormalities. The DeltaVT relaxation during the PBTI recovery period induced by bulk trapping/de-trapping is believed to be oxygen vacancies related, and can be suppressed either by reducing dielectric intermixing with lower laser anneal powers (La above or below HK), or by increasing the oxygen concentration, i.e., TaCNO metal electrode instead of TaCN (La above HK). Putting La below HK can result in a similar VT tune-ability with less thermal budget for intermixing with the IL (with superior PBTI), without loss of current drive-ability. We propose Ta2C/HK/LaO/IL + LLP anneals as an optimum nFETs stack configuration for practical CMOS integration.

Investigation of aged organic solar cell stacks by cross-sectional transmission electron microscopy coupled with elemental analysis

Polymer solar cells are of great interest as candidates for future low-cost and lightweight energy sources. One of the major reliability problems of these devices is the thermal instability of the blend morphology typically composed of poly(3-hexylthiophene) and [6,6]-phenyl-C61-butyric acid methyl ester (P3HT and PCBM, respectively). Phase segregation of the blend has been extensively investigated by transmission electron microscopy (TEM) on free-standing films. In this study, we investigate in cross-section the morphology reorganization of P3HT:PCBM layers confined between poly(3,4-ethylenedioxythiophene)poly-(styrenesulfonate) (PEDOT:PSS) and a metal electrode similar to functional solar cell devices. The strengths of different TEM imaging and compositional analysis modes for the investigation of organic solar cells is illustrated by studying the evolution of the material stack with ageing conditions. Combining TEM imaging of the layer stack with energy-dispersive X-ray and energy loss electron spectroscopy, we not only gain insight into the phase segregation process but also explore the interdiffusion in the layer stack. More than 100xa0°C annealing leads to the formation of elongated protrusions ranging 100–500xa0nm. Thinning of the neighboring areas indicates lateral diffusion in the stack. Interestingly, the metal cathode remains still conformal over these large aggregates. The particles protrude through the metal layer only after prolonged (>100xa0h) annealing at higher temperatures when they reach several micrometer in height and are identified as crystalline PCBM-like material. Hence, almost full phase separation occurs by PCBM agglomeration and diffusion over large distances. Elemental analysis confirms that diffusion of the electrode materials (In, Sn and Yb) into the P3HT:PCBM stack remains below the detection limit.

Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering

We report the lowest leakage achieved to date in sub-0.5 nm EOT MIM capacitors compatible with DRAM flows, showing for the first time a path enabling scalability to the 3X nm node. A novel stack engineering consisting of: 1) novel controlled ultrathin Ru oxidation process, 2) TiO<inf>x</inf> interface layer, is used for the first time to achieve record low Jg-EOT in MIM capacitors using ALD Sr-rich STO high-k dielectric and thin Ru bottom electrode. Record low Jg of 10⁻⁶ A/cm² (10⁻⁸ A/cm²) is achieved for EOT of 0.4 nm (0.5 nm) at 0.8 V. Our data is compared favorably (> 100× Jg reduction at 0.4 nm) to previous best values in literature for MIMcaps with ALD dielectrics.

Properties of Ultrathin High Permittivity ( Nb1 − x Ta x ) 2O5 Films Prepared by Aqueous Chemical Solution Deposition

Ultrathin Nb1�xTax2O5 films, with thicknesses from 3t o 25 nm, were deposited by chemical solution deposition starting from aqueous precursor solutions. The film’s dielectric properties were characterized by capacitance–voltage and current–voltage measurements. Permittivities ranged from 20 to 31 after annealing at 600°C, with the highest value obtained for pure Nb2O5. With increasing Nb content, increasing leakage currents were observed. The crystallization temperature was determined by in situ X-ray diffraction measurement for films with 15 nm thickness: Nb2O5 was crystalline as deposited 600°C, while the crystallization temperature of solid solutions increased with increasing Ta content, up to 875°C for pure Ta2O5. NbTaO5 showed a marked increase in permittivity from 27 to 38 after crystallization anneal at 600 and 800°C, respectively. For Nb2O5, no significant difference in permittivity was observed between amorphous and crystalline layers.

Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors

Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type FinFETs and p-type Si1-xGex-channel pFETs, and relies mainly on TCAD results. It will be shown that on n-FinFETs, tensile stressed Contact EtchStop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. Tensile stressed gates are shown to be an effective stressor on gatefirst n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. For pFETs with strained Si1-xGex-channels like the Implant-Free Quantum Well (IFQW) FET, it will be shown that elastic relaxation during source/drain recess is an important factor that reduces the effectiveness of Si1-yGey source/drain stressors. For scaled technologies, omitting the source/drain recess altogether and opting for a raised source/drain scheme is preferred. In IFQW pFETs, dependence of the drive current on transistor width is an important concern. It will be shown that a Si1-yGey source/drain reduces the layout dependence of IFQW FETs, an effect that is enhanced further when combined with a gate-last integration scheme.

High Performance Oxide Diode

We report the fabrication of oxide diodes with size down to 40×40nm 2 which could be used for selector applications in high density nonvolatile memory arrays. The diodes consist of VO2 and TiO2 while the electrodes are TiN. The diodes show current density up 10 5 A/cm 2 and ideality factors less than 2.3. Turn-on time is shorter than 5ns, and cycling endurance higher than 10 9 cy.