M. Schaekers

The VO2 interface, the metal-insulator transition tunnel junction, and the metal-insulator transition switch On-Off resistance

Transition metal compounds showing a metal-insulator transition (MIT) show complex behavior due to strongly correlated electron effects and offer attractive properties for nano-electronics applications, which cannot be obtained with regular semiconductors. MIT based nano-electronics, however, remains unproven, and MIT devices are poorly understood. We point out and single out one of the major hurdles preventing MIT-electronics: obtaining a high Off resistance and high On-Off resistance ratio in an MIT switch. We show a path toward an MIT switch fulfilling strict Off and On resistance criteria by: (1) Obtaining understanding of the VO2-interface, a protoypical MIT material interface. (2) Introducing a MIT tunnel junction concept to tune switch resistances. In this junction, the metal or insulating phase of the MIT material controls how much current flows through. Adapting the junctions parameters allows tuning the MIT switchs Off and On resistance. (3) Providing proof of principle of the junction and its...

High-k Dielectrics and Metal Gates for Future Generation Memory Devices

The requirements and development of high-k dielectric films for application in storage cells of future generation flash and Dynamic Random Access Memory (DRAM) devices are reviewed. Dielectrics with k-value in the 9-30 range are studied as insulators between charge storage layers and control gates in flash devices. For this application, large band gaps (> 6 eV) and band offsets are required, as well as low trap densities. Materials studied include aluminates and scandates. For DRAM metal-insulator-metal (MIM) capacitors, aggressive scaling of the equivalent oxide thickness (with targets down to 0.3 nm) drives the research towards dielectrics with k-values > 50. Due to the high aspect ratio of MIMCap structures, highly conformal deposition techniques are needed, triggering a substantial effort to develop Atomic Layer Deposition (ALD) processes for the deposition of metal gates and high-k dielectrics. Materials studied include Sr and Ba-based perovskites, with SrTiO3 as one of the most promising candidates, as well as tantalates, titanates and niobates.

Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering

We report the lowest leakage achieved to date in sub-0.5 nm EOT MIM capacitors compatible with DRAM flows, showing for the first time a path enabling scalability to the 3X nm node. A novel stack engineering consisting of: 1) novel controlled ultrathin Ru oxidation process, 2) TiO<inf>x</inf> interface layer, is used for the first time to achieve record low Jg-EOT in MIM capacitors using ALD Sr-rich STO high-k dielectric and thin Ru bottom electrode. Record low Jg of 10⁻⁶ A/cm² (10⁻⁸ A/cm²) is achieved for EOT of 0.4 nm (0.5 nm) at 0.8 V. Our data is compared favorably (> 100× Jg reduction at 0.4 nm) to previous best values in literature for MIMcaps with ALD dielectrics.

VO2, a Metal-Insulator Transition Material for Nanoelectronic Applications

Nanoelectronic Applications K. Martens, I. P. Radu, G. Rampelberg, J. Verbruggen, S. Cosemans, S. Mertens, S. Xiaoping, M. Schaekers, C. Huyghebaert, C. Detavernier, S. De Gendt, M. Heyns, J. Kittl a IMEC, Kapeldreef 75, Leuven, Belgium b ESAT Dept., KULeuven, Leuven, Belgium c Physics Dept., K. U. Leuven, Leuven, Belgium d Dept. of Solid State Sciences, UGent, Gent, Belgium e Chemistry Dept. KULeuven f Materials Engineering Dept., KULeuven

Cost-effective cleaning for advanced Si-processing

The effect of various metal contaminants on the thin gate oxide integrity is investigated and a classification is made according to their final position in the structure. A simplified cleaning strategy is presented which is highly performant and at the same time cost-effective and has less environmental impact than the traditional cleaning sequences. Finally, a novel environmentally friendly ozone/DI-water process for the removal of photoresist and organic post-etch residues is proposed.

Dummy oxide removal in high-K last process integration how to avoid silicon corrosion issue

The industry has diverged into two main approaches for high-k and metal gate (HKMG) integration. One is the so called gate-first. The other is gate-last, also called replacement metal gate (RMG) where the gate electrode is deposited after junctions formation and the high-k gate dielectric is deposited in the beginning of the flow (high-k first-RMG) or just prior to gate electrode deposition (high-k last-RMG) [1-. We can distinguish two RMG process flows called either high-k first or high-k last. In RMG high-k first, poly silicon is removed on top of a TiN etch stop layer whereas on high-k last poly silicon is removed on top of a dummy oxide layer. This dummy oxide has also to be removed in order to redeposit a novel high-k and work function metal (Figure 1).