Papu D. Maniar

A model for electrical conduction in metal‐ferroelectric‐metal thin‐film capacitors

Time‐zero current‐voltage characteristics and time‐dependent current behavior of metal‐ferroelectric‐metal (Pt‐PZT‐Pt) capacitor structures have been studied. Under constant‐voltage stressing, the current density through the 1500‐A‐thick lead‐zirconate‐titanate (PZT) film exhibits a power‐law dependence on time, with the exponent (∼0.33) independent of temperature and voltage. Electrode material dependence of current density indicates that the conventional model of trap‐limited single‐carrier injection over nonblocking contacts is inadequate to explain the time‐zero current. A change in top electrode material from Pt to In leads to the observation of work‐function‐driven Schottky contacts between the metal and ferroelectric. The current‐voltage characteristics fit a two‐carrier injection metal‐semiconductor‐metal model incorporating blocking contacts, with distinct low‐ and high‐current regimes (PZT is assumed to be p‐type and trap‐free in this model). Temperature‐dependent I‐V measurements indicate a Pt‐...

Electrical characteristics of paraelectric lead lanthanum zirconium titanate thin films for dynamic random access memory applications

Paraelectric lead lanthanum zirconium titanate (PLZT) films, 150 nm thick, were deposited using a spin‐coat, sol‐gel process followed by a 650 °C oxygen anneal. X‐ray diffraction indicated complete conversion to the perovskite phase. Sputter‐deposited platinum electrodes were employed with the PLZT films to form thin‐film capacitors with the best combination of high charge storage density (26.1 μC/cm2 at 3 V and 36.4 μC/cm2 at 5 V) and leakage current density (0.2 μA/cm2 at 3 V and 0.5 μA/cm2 at 5 V ) reported to date. The electrical characteristics of these thin‐film capacitors meet the requirements for a planar bit cell capacitor for 64‐Mbit dynamic random access memories.

Materials interactions in the integration of PZT ferroelectric capacitors

Abstract Investigations of materials interactions that complicate the integration of PZT ferroelectric capacitors into CMOS technologies are discussed. These include interactions within the Pt/Ti electrodes structure, the reactions of sol-gel deposited PZT during crystallization with various underlying dielectrics (SiO2, Si3N4, Al2O3, and TiO2), and the impact of other integrated circuit processes on fabricated capacitors.

Fabrication and characterization of InGaP/GaAs heterojunction bipolar transistors on GOI substrates

In this letter, we report the first demonstration of InGaP/GaAs heterojunction bipolar transistors (HBTs) on germanium-on-insulator (GOI) substrates. We have performed physical characterization of the epitaxial layers to verify the high quality of the III-V epitaxial material grown on the GOI substrates and performed dc characterization of large-area InGaP/GaAs HBTs fabricated on the substrates. The InGaP/GaAs HBTs realized on GOI substrates were compared with identical devices grown on bulk germanium substrates and similar devices on semi-insulating GaAs substrates.

Impact of Backend Processing on Integrated Ferroelectric Capacitor Characteristics

Integration of a ferroelectric capacitor module in a standard CMOS process subjects the ferroelectric to various ambients during backend processing, some of which can render the ferroelectric essentially non-operational for NVRAM applications. Post-crystallization processing of sol-gel deposited integrated ferroelectric PZT capacitors in the presence of hydrogen-containing, reducing ambients is observed to degrade the nonvolatile polarization. Low-pressure hydrogen anneals at temperatures as low as 200°C substantially degrade the nonvolatile polarization while the DRAM polarization remains roughly constant. Leakage current drops by one order of magnitude and fatigue is accelerated. A ferroelectric capacitor module can be integrated with minimal degradation with careful modifications in the backend processing.

High-permittivity lead-based perovskite dielectrics for DRAM applications

Abstract Suppression of the nonvolatile polarization in lead zirconate titanate films by La doping or by use of films 100 nm or less in thickness provides the highest charge storage densities yet observed. These films also satisfy leakage current density and TDDB requirements for very high density DRAMs, and show good resistance to fatigue.

Analyses of Pt/Ti Electrodes for Plzt Capacitors

A suitable choice of an electrode material is important for an acceptable electrical contact to a high-permittivity dielectric, such as PLZT. A material which does not form a low-permittivity oxide is necessary, since these dielectrics generally require high temperature deposition or annealing in an oxidizing environment. Platinum, which is one of the few metals that satisfy this requirement, has been widely employed for contacting PLZT. However, for integrated circuit applications, an adhesion layer must be superposed between Pt and the substrate, and Ti is used frequently. Therefore, we have investigated the Pt/Ti combination to determine its suitability as an electrode for contacting PLZT. Using x-ray diffraction, Rutherford backscattering spectrometry, Auger electron microscopy, and scanning electron microscope techniques, interdiffusion of Pt/Ti bilayers has been investigated. Pt/Ti films with or without PLZT overlay were annealed in either O 2 or N 2 ambients or in N 2 followed by O 2 . Annealing temperatures varied from 500 to 800 °C. It was observed that the anneal ambient has a marked effect on the interdiffusion processes, the reaction products, the morphology of the structures, and the crystallization of PLZT.

Integration of ferroelectric capacitor technology with CMOS

Ferroelectric technology has several desirable features for low-power nonvolatile memories including low operating voltages (read and write as low as 1.5 V), high-speed write operation (intrinsic switching times <2 ns), long-term endurance (>10/sup 13/ read/write cycles), and small cell size (potentially near DRAM densities). Realization of practical memories employing ferroelectric technology requires successful integration with CMOS. However, very little has been reported on the process integration issues unique to ferroelectric technology. This paper is the first detailed report of these integration issues. The paper discusses the impact of CMOS backend processing on ferroelectric capacitors as well as the effect of capacitor fabrication on transistor characteristics.<<ETX>>

32.5L: Late-News Paper: Multitouch Pixilated Force Sensing Touch Screen

In this paper we discuss the advantages of direct touch detection with pixilated force sensing in eliminating false readings and improving accuracy in locating touch centers. We also show the properties of the transparent force sensing layer and demonstrate a 3.5 inch prototype touch panel that senses both location and force of touch actions and is multitouch capable.