Parrish Ralston

High-Voltage capacitance measurement system for SiC power MOSFETs

Adequate modeling of a power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is dependent on accurate characterization of the inter-electrode capacitances. With the advent of high-voltage silicon carbide (SiC) power MOSFETs, it has become important to develop a measurement system that can perform and record high-voltage capacitance versus voltage measurements on these devices. This paper describes a measurement apparatus that safely and accurately allows high voltage capacitance-voltage (CV) measurements to be performed. The measurements are based on conventional LCR (Inductance (L), Capacitance (C), and Resistance (R)) meter CV techniques but with added circuitry to interface the LCR meter to high voltage bias sources. The effects of the added circuitry are studied theoretically, and the CV measurement accuracy is verified with experimentation. High voltage capacitance voltage measurements are presented for both silicon and SiC power MOSFETs.

A W-band micro coaxial passive monopulse comparator network with integrated cavity-backed patch antenna array

An integrated W-band passive monopulse comparator network is constructed using four rat-race hybrids, designed using the Polystrata™ 3-D sequential micromachining process. The comparator network has a simulated azimuth null of 44.6 dB and elevation null of 44.4 dB. The network is monolithically integrated with an array of cavity backed patch antennas and diode detectors for measurement purposes. An azimuth null of 31.4 dB and an elevation null of 22.5 dB are measured at 93.5 GHz.

Test and verification of micro coaxial line power performance

This paper presents the characterization of rectangular micro-coaxial transmission lines assembled in a high power test system. In addition to straight transmission lines, vertical solder transitions between stacked layers of rectangular coax are presented. These test assemblies utilize standard integration techniques and components: wire bond and flip-chip transitions and edge coaxial connectors. Assembled coax lines were tested at continuous wave power levels as high as 200 W at a frequency of 2 GHz. High frequency performance of the test assemblies is maintained throughout high power testing. Thermal models developed using a 3-D finite element method are utilized to understand limitations of micro-coaxial transmission lines at higher frequencies.

Liquid–Metal Vertical Interconnects for Flip Chip Assembly of GaAs C-Band Power Amplifiers Onto Micro-Rectangular Coaxial Transmission Lines

Prior work has demonstrated a new process utilizing room-temperature liquid metal, Galinstan, as an interconnect material for flip-chip bonding. This interconnect forms a flexible bond between chips and carriers, and, therefore, a flip-chip assembly using this technology is much less susceptible to thermomechanical stresses. This paper applies this concept to interconnect GaAs MMIC chips to 3-D Polystrata transmission-line structures. Passive assemblies are utilized to model, test, and verify liquid-metal interconnections, giving average losses per liquid-metal transition of about 0.11 dB out to 26.5 GHz, low parasitics per transition, and demonstrated reliability after temperature cycling. A prefabricated GaAs MMIC chip is postprocessed for liquid-metal assembly. Measured results show, over the MMICs 4.9-8.5-GHz frequency range, the systems overall reduction in gain of the MMIC is 1.4 dB or 0.7 dB per RF transition as compared with direct probing of the MMIC chip.

Low Loss, High Performance 1-18 GHz SPDT Based on the Novel Super-Lattice Castellated Field Effect Transistor (SLCFET)

A low loss, high isolation, broadband RF switch has been developed using a novel type of field effect transistor structure that exploits the use of a super-lattice structure in combination with a three dimensional, castellated gate to achieve excellent RF switch performance. Using an AlGaN/GaN super-lattice epitaxial layer, this Super-Lattice Castellated Field Effect Transistor (SLCFET) was used to build 1-18 GHz SPDT RF switches. Measured insertion loss of the SPDT at 10 GHz was -0.4 dB, with -35 dB of isolation and -23 dB of return loss, along with a measured linearity OIP3 value 62 dBm and a P0.1dB of 34 dBm.

Liquid Metal Vertical Interconnects for Flip-Chip Assembly of GaAs C-Band Power Amplifiers onto Micro-Rectangular Coaxial Transmission Lines

Prior work has demonstrated a new process utilizing room temperature liquid metal, galinstan, as an interconnect material for flip chip bonding. This interconnect forms a flexible bond between chips and carriers and therefore a flip chip assembly using this technology is much less susceptible to thermomechanical stresses. This paper applies this concept to interconnect MMIC chips to 3D Polystrata transmission line structures. A prefabricated GaAs MMIC chip is post processed for liquid metal assembly. Measured results show, over the MMICs 4.9 - 8.5 GHz frequency range, the systems overall reduction in gain of the MMIC is 1.4 dB or 0.7dB per RF transition as compared to direct probing of the MMIC chip.

Liquid metal vertical interconnects for RF flip-chip assembly

This paper describes a new process for using room temperature liquid metals as the interconnect material for flip chip bonding. The proposed liquid metal interconnects are not susceptible to damage caused by thermo-mechanical stress and are therefore an attractive alternative to solid phase solder bumps. A new interconnect structure is presented involving a patterned underfill dielectric material to contain the liquid metal on the bottom carrier, and electroplated pins on the top chip to mate with the socket and make contact with the liquid metal. RF and DC measurements were performed on the liquid metal transition showing an insertion loss of ≪0.5dB up to 20 GHz.

Advances in the Super-Lattice Castellated Field Effect Transistor (SLCFET) for wideband low loss RF switching applications

The Super-Lattice Castellated Field Effect Transistor (SLCFET) uses a super-lattice in the channel region to form multiple parallel current paths in conjunction with castellations etched into that super-lattice to provide a sidewall gate structure. The sidewall gate permits the gate applied electric field to penetrate between the parallel 2DEG layers, allowing the carriers to be depleted out prior to avalanche breakdown within the material, as would occur with a conventional gate structure. Using an AlGaN/GaN super-lattice, we report on this method as a way to scale RF switch performance, decreasing ON resistance without significantly increasing OFF capacitance, with a median measured ON resistance of 0.38 Ω-mm and a median measured OFF capacitance of 0.21 pF/mm, leading to an RF switch figure of merit, FCO=2.0 THz. 90/10 and 10/90 fall and rise times for the SLCFET have been measured to be faster than 100 nsec, while the RF power handling for a series SLCFET has been measured at 10 GHz to be greater than 10 W without loss compression. Wideband SPDT RF switch performance over a 0.5-20 GHz bandwidth with <;|-0.3| dB of insertion loss and >|-30| dB of isolation has been achieved.

TSV-Last, Heterogeneous 3D Integration of a SiGe BiCMOS Beamformer and Patch Antenna for a W-Band Phased array Radar

We report a TSV-last, heterogeneous 3D integration process for millimeter wave solid state tiles for use in the demonstration of a W-band active electronically scanned array (AESA) radar system. Each phased array tile consists of a high speed SiGe BiCMOS beamformer chip, vertically integrated with an advanced, multi-metallization level glass substrate which includes an RF interposer and a patch antenna array. This paper will briefly describe the SiGe and glass circuit layers, along with the main components of the 3D integration processing and assembly. Electrical testing of the SiGe and glass chips was conducted at various points during the integration processing, including DC and RF measurements after the two chips were bonded together. Additionally, DC testing of TSV chains was completed along with thermal cycling. The results of this work indicated a successful initial prototype demonstration of 3D heterogeneous integrated phased array tiles, which can be used for a multi-tile subarray assembly and subsequent sensor system demonstration.

Heterogeneous flip-chip assembly of a GaAs C-band power amplifier MMIC using liquid metal vertical interconnects

A new process utilizing room temperature liquid metals as interconnect material for flip chip assembly of active circuits has been demonstrated. These interconnects form flexible bonds between chips of heterogeneous materials and therefore flip clip assembly built with this configuration is not susceptible to thermomechanical stresses. A prefabricated GaAs MMIC chip is post processed to integrate liquid metal assembly structures. For the operation frequency of the MMIC between 4.9 – 8.5 GHz, average gain of the assembly is greater than 20 dB with an average transition loss of less than 1.8 dB.