Pascal A. Nsame

Circuit-dependent F MAX , Power and Process optimization to improve product Reliability, Availability and Serviceability

A fully functional PowerPC476FP SoC communication processor with 4MB eDRAM System Cache achieving 2GHz/Core, in a 4 × 2.5DMIPS/Core/MHz configuration is qualified using physics-of-aging models in a 45nm SOI CMOS technology node including a logic and deep-trench (DT) eDRAM optimized semiconductor process. A novel circuit-depend F<;sub>MAX<;/sub>, Power, and Process optimization methodology that resolves technology reliability limitations (including Stress Migration, EM, BTI, HCI, TDDB, Defects, Package) without product burn-in, while delivering a 9.26% improvement per bin in energy-efficiency across 16 bins and up to 43.9% reduction in failure rate compare to equivalent circuits without the novel optimization methodology is described. Measured results show functional operation with a voltage range of 0.75V to 1.125V, a temperature range of -40C to 125C, speed of 1.8+ GHz at 0.96V, 110C and 90-100% yield performance, for a product lifetime specification of 88KPOH & 2750 ON/OFF cycles. These results demonstrate the highest reliability-aware functional performance reported to date with a 45nm nominal process at 0.9V for a 32-bit Quad-Core communication processor with asymmetric and scalable architecture while achieving the highest reported enterprise-level energy efficiency compare to Quad-Core communication processors in the same class. The technical contributions in this work enables a growing industry trend towards multi-radio ultra-compact stackable base stations designed to drastically reduce the entry price level per base station, enhance scalability and up-gradeability, significantly lower power consumption and enhance flexibility.

Embedded powerPC 405 & 440-based SoC product qualifications on 45°-rotated substrates

We discuss functionality, performance, power and reliability evaluations of the worlds first SoC products fabricated using IBM 90nm technology on a 45°-rotated substrate. We have demonstrated reliable product operational lifetimes with up to 12% improved across die delay variability including 30% product performance improvement and 33% leakage reduction over nonrotated substrate.

SSCS-Green Mountain Organizes 17th IEEE North Atlantic Test Workshop, IEEE NATW Special Session on Solid-State Circuits & System Test Held on 14–16 May, 2008

Sponsored by the SSCS-Green Mountain chapter on May 14-16, 2008, the 17th annual North Atlantic Test Workshop (NATV) included a special session on solid-state circuits and system test focused on advances in built-in self-test for 65nm and 45nm nodes, adaptive test, and on-product reliability testing. Featured presenters were IBMs Mike Ouellette, Matt Grady and Kevin Stawiasz.

Multi-processor SoC integration: a case study on BlueGene/L

We investigate the scalability, architectural requirements, and performance characteristics of high performance systems. We use the BlueGene/L (BG/L) project as a case study for deep computing applications. This massively parallel system of 65,536 nodes with autonomic features is based on a new architecture that exploits system-on-a-chip (SoC) technology to deliver a target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). BG/L is operational at a price/performance and a power consumption/performance targets unobtainable with published conventional architectures.