Y. Bert

Impact of hump effect on MOSFET mismatch in the sub-threshold area for low power analog applications

Analog circuit designs are often biased to work in sub-threshold mode with good gate-source voltage matching performances. Depending on the process, hump effect may change the MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. To model the hump effect, two narrow parasitic MOS are introduced in parallel with the main device. To accurately simulate matching degradation in sub-threshold mode, these parasitic transistors, in case of hump effect, have to be considered.

Gate Voltage Matching Investigation for Low-Power Analog Applications

On CMOS technology, some process steps can create a parasitic phenomenon named “hump effect.” This parasitic effect can have a strong impact on gate voltage matching of differential pairs and, as a consequence, on analog circuit performances. In this context, several solutions to limit or remove this hump effect are proposed and described. Silicon data obtained at package and wafer levels for different temperatures are analyzed.

Active “multi-fingers”: Test structure to improve MOSFET matching in sub-threshold area

Low power analog applications are often designed under threshold and can be degraded by hump effect. This effect is explained through device dimensions and body bias studies. A MOSFET matching improvement in sub-threshold area is demonstrated with active “multi-fingers” test structure.

771mV, 173nA, 90nm CMOS resistorless trimmable voltage reference

A low power voltage reference generator operating with a supply voltage ranging from 1.6V to 3.6V has been implemented in a 90-nm standard CMOS process. The reference is based on MOSFETs biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6V and at 125°C is 173nA. It provides an 771mV voltage reference. A temperature coefficient of 7.5ppm/°C is achieved at best and 39.5ppm/°C on average, in a range from −40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. The total block area is 0.03mm2.

A 90-nm CMOS resistor-free compact trimmable voltage reference for ultra-low power low cost applications

A low power voltage reference generator operating with a supply voltage ranging from 1.6V to 3.6V has been implemented in a 90-nm standard CMOS process. The reference is based on MOSFETs that are biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6V and at 125°C is 173nA. It provides an 771mV voltage reference. A temperature coefficient of 7.5ppm/°C is achieved at best and 39.5ppm/°C on average, in a range from −40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. The total block area is 0.03mm2.

Octagonal MOSFET: Reliable device for low power analog applications

Low power analog circuits needs large and short MOSFETs biased in the sub-threshold area with good performances in terms of matching. In order to reach these specifications, octagonal transistors are proposed. Due to their design, these transistors avoid hump effect. As a consequence, gate-source voltage matching under-threshold is always at its best level. Moreover, the paper shows the device robustness to hot carrier stress is improved on octagonal NMOS; VT matching degradation due to hot carrier stress is also improved with an octagonal design.

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress

Device degradation modelling is more and more important for reliable circuit design. On MOSFET, the threshold voltage drift in time can lead to circuit performance degradation. In this study, VT shift due to Hot Carrier Injection stress is accelerated on small width devices. VT matching is also degraded during stress as a function of VT deterioration. This width dependence allows explaining gate voltage matching behavior in the sub-threshold area used in low power analog applications.

Poly-Silicon gate pre-doping implantation impact on MOSFET matching performances

This paper demonstrates how poly-Silicon gate pre-doping implantation impacts MOS matching performances. Measurements are performed on test structures (MOS pairs / capacitors) and analog circuits, using five different processes with pre-doping implantation energy variation (from 35 to 10 KeV) and tilt variation (7° and 25°). TCAD simulations validate a channel counter-doping due to high pre-doping implantation energy causing mismatch degradation.

173nA-7.5ppm/°C-771mV-0.03mm 2 CMOS resistorless voltage reference

A low power voltage reference generator operating with a supply voltage ranging from 1.6V to 3.6V has been implemented in a 90-nm standard CMOS process. The reference is based on MOSFETs biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6V and at 125°C is 173nA. It provides an 771mV voltage reference. A temperature coefficient of 7.5ppm/°C is achieved at best and 39.5ppm/°C on average, in a range from −40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. The total block area is 0.03mm2.