Patrice Parris

Integration of multi-voltage analog and power devices in a 0.25/spl mu/m CMOS + flash memory process

This paper presents the integration of multivoltage analog and power devices into a 0.25 /spl mu/m CMOS + flash memory process based on Motorolas HiPerMOS/spl trade/ platform. A variety of MOSFETs and BJTs with breakdown voltage ranging from 10 V to more than 40 V, as well as high sheet resistance precision resistors, have been fabricated with the addition of only 3 simple masked implants to the existing process.

DC substrate coupling between LDMOS and CMOS devices in Hyperintegration I technology

The DC substrate coupling between NLDMOS and CMOS inverter has been studied in Hyperintegration I technology using conventional protection schemes. Using N-well rings and substrate contact rings sufficiently spaced from the injector as well as the inverter, latchup can be avoided up to output currents of 4 A.

Single poly EEPROM for smart power IC's

Smart power integrated circuits need low density memory for applications such as trimming, IC customization, system addresses, and part traceability with few program/erase cycles. Memory solutions must be low cost and demonstrate high reliability in automotive environments. Programmability in the application is an advantage. We have developed a single poly EEPROM that meets these requirements and in addition gives significant die area savings over traditional low cost memory techniques.