Yee-Chaung See

A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications

A leading edge 90nm bulk CMOS device technology is described in this paper. In this technology, multi Vt and multi gate oxide devices are offered to support low standby power (LP), general-purpose (G or ASIC), and high-speed (HS) system on chip (SoC) applications. High voltage I/O devices are supported using 70/spl Aring/, 50/spl Aring/, and 28/spl Aring/ gate oxide for 3.3V, 2.5V, and 1.5-1.8V interfaces, respectively. The backend architecture is based on nine levels of Cu interconnect with hot black diamond (HBD) low-k dielectric (k<=3.0).

A novel LDMOS structure with a step gate oxide

High performance power device is essential for power integrated circuits and discrete power devices. A novel LDMOS structure with step gate oxide is proposed for breakdown voltage or on state resistance (Ron) improvement. The step gate oxide is introduced on the LDMOSs drift region. The thicker step gate oxide can improve device breakdown voltage without significantly affecting other device electric parameters. As a result, drain can be pulled back and self-aligned to the gate. This can significantly reduce device drift region and improves device on state resistance. This approach is different from conventional approach (with or without field oxide on the drain side) which drain is not self-aligned to the gate.

High-performance SiGe epitaxial base bipolar transistors produced by a reduced-pressure CVD reactor

High-performance Si and SiGe epitaxial base bipolar transistors have been fabricated using a commercially available, reduced pressure, epitaxial reactor. The SiGe devices exhibit exceptional Early voltages in the range of 400-500 V, and an f/sub T/ of 31 GHz with a BV/sub CEO/ of 7.6 V and BV/sub CBO/ of 16 V. These results demonstrate that SiGe has potential as a commercially viable technology for analog, digital, and mixed-signal applications.<<ETX>>

Poly-gate sidewall oxidation induced submicrometer MOSFET degradation

The effect of poly-gate sidewall oxidation on short-channel MOSFET behavior is examined. The gain, threshold voltage, and apparent electrical channel length are shown to be very sensitive to the location of the n/sup -/ junction edge with respect to the poly-gate edge for a lightly-doped-drain NMOS transistor. New guidelines for the design of submicrometer MOSFETs based on an analysis of the sidewall oxidation of the polysilicon after gate definition are proposed.<<ETX>>

A high-performance 0.5- mu m BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5- mu m BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 mu m/sup 2/ by creating self-aligned bit-sense and V/sub ss/ contacts. A WSi/sub x/ polycide emitter n-p-n transistor with an emitter area of 0.8*2.4 mu m/sup 2/ provides a peak cutoff frequency (f/sub T/) of 14 GHz with a collector-emitter breakdown voltage (BV/sub CFO/) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f/sub T/ and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process. >

A high performance 0.5 mu m BiCMOS triple polysilicon technology for 4 Mb fast SRAMs

A high-performance 0.5 mu m BiCMOS technology has been developed which uses a triple polysilicon process architecture for a 4 Mb fast SRAM class of products. Three layers of polysilicon are used to achieve a compact four transistor cell size that is less than 20 mu m/sup 2/ by creating self-aligned bit-sense and Vss contacts to the four transistor cell. A WSi/sub x/ polycide emitter n-p-n transistor has been implemented with an emitter area of 0.8*2.4 mu m/sup 2/ and peak cutoff frequency (f/sub T/) of 14 GHz. A selectively ion implanted collector has been used to compensate the base channeling tail as well as to increase knee current and f/sub T/, while maintaining a collector to emitter breakdown voltage of 6.5 V. A minimum ECL gate delay of 115 ps has been achieved at a gate current of 400 mu A.<<ETX>>

A high-performance sub-half micron CMOS technology for fast SRAMs

An advanced high-performance sub-half-micron technology for fast CMOS SRAMs (static RAMs) has been developed. Features of this thin-well process include: an aggressive interwell isolation module, framed-mask poly-buffered LOCOS isolation (FMPBL), a 125-AA gate oxide, dual n/sup +//p/sup +/ implanted polysilicon gates, titanium salicide, two levels of polysilicon, TiN metallization barriers, a poly plug option, and up to three layers of metallization. An interwell isolation process allows scaling of the n/sup +/ to p/sup +/ space to less than 2 mu m. Active transistor design is optimized to reduce the polysilicon gate birds beak and LDD (lightly doped drain) underdiffusion. Discrete transistor lifetimes for hot carrier degradation are in excess of 10 years of 3.3-V operation. A 16 K*4 SRAM displays no parametric shifts after HCl stressing for 1000 h at 7 V and 0 degrees C. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are obtained.<<ETX>>

A high-performance half-micrometer generation CMOS technology for fast SRAMs

An advanced, high-performance, half-micrometer generation technology has been developed for fast CMOS SRAM circuits. This process features an aggressive interwell isolation module which allows scaling of the n/sup +/ to p/sup +/ space to less than 2 mu m and an advanced framed-mask poly-buffered LOCOS isolation (FMPBL) which reduces field oxide encroachment and the transistor narrow-width effect and provides a 1.2- mu m active pitch. Transistors are fabricated with a 125-A gate oxide and a dual n/sup +//p/sup +/ source/drain implanted polysilicon gates to provide excellent short-channel behavior down to 0.3- mu m effective channel length. Transistor design is optimized to reduce the polysilicon gate birds beak and lightly doped drain (LDD) underdiffusion. For PMOS transistors, boron diffusion through the gate oxide is minimized by replacing BF/sub 2/ with B/sup 11/ for the p/sup +/ S/D implant. A titanium salicide process provides strapping between n/sup +//p/sup +/ polysilicon gates and lower sheet and contact resistances. The back-end features three levels of metallization and polysilicon contact plugs. Discrete transistor lifetimes for DC hot-carrier degradation are in excess of 10 years at 3.3-V operation. A 16 K* 4 SRAM displayed no parametric shifts after hot-carrier stressing for 1000 h at 7-V and 0 degrees C. This is consistent with a lifetime of greater than 10 years at 3.3-V operation. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are achieved. >

Integration of a double-polysilicon emitter-base self-aligned bipolar transistor into a 0.5- mu m BiCMOS technology for fast 4-Mb SRAM's

The single-polysilicon non-self-aligned bipolar transistor in a 0.5- mu m BiCMOS technology has been converted into a double-polysilicon emitter-base self-aligned bipolar transistor with little increase in process complexity. Improved bipolar performance in the form of smaller base resistance and base-collector capacitance, larger knee current, higher peak cutoff frequency, and shorter ECL gate delay has been demonstrated. This technology will prove useful in meeting the requirements for higher performance in fast, high-density, SRAM circuits. >

Characteristics of a poly-silicon contact plug technology

Summary form only given. Polysilicon plug technology takes advantage of the desirable properties of LPCVD polysilicon (i.e. conformal step coverage, smooth texture, good etchability) to planarize submicron contacts. In addition, sputtered and CVD barrier metal layers are utilized to ensure good ohmic contact and maintain a low-resistance plug. It is shown that the polysilicon plugs completely fill the contact holes and provide a nearly planar surface for the sputtered aluminum. In addition, the RIS+CVD TiN barrier is highly conformal for all observed contact sizes. The specific contact resistance to n/sup +/ and p/sup +/ doped silicon was found to be less than 5*100/sup -7/ Omega -cm/sup 2/. To titanium silicide, the contact resistance dropped to below 2*10/sup -8/ Omega -cm/sup 2/. The composite resistivity of the polysilicon plug plus CVD and RIS TiN barrier was less than 5*100/sup -4/ Omega -cm/sup 2/. Shallow junction, contact-intensive diode structures exhibited good breakdown voltages and leakage current below 5 nA/cm/sup 2/. These results demonstrate a reproducible contact plug technology suitable for advanced MLM CMOS circuits.<<ETX>>