Patrick H. Keys

Kinetics of Shallow Junction Activation: Physical Mechanisms

Forming highly active shallow junctions is a key component enabling low external resistance and high transistor performance. Millisecond flash or scanning laser anneals can be used to contain diffusion and optimize activation, either directly by leveraging temperatures exceeding 1200C, or in combination with non-equilibrium processes such as amorphization plus solid phase epitaxy or liquid phase epitaxy. Diffusionless profiles can be obtained, but may not be optimal for devices. Consideration of deactivation physics is crucial to incorporation of any process leveraging superactive doping, since relaxation of doping is frequently very rapid, and may be crucially influenced by implant damage effects. Developing an understanding of dominant mechanisms is essential for the exploitation of millisecond or faster anneals to form superactive doping

Modeling of ultrahighly doped shallow junctions for aggressively scaled CMOS

This paper presents an integrated modeling approach to address diffusion and activation challenges in sub-90 nm CMOS technology. Co-implants of F and Ge are shown to reduce diffusion rates and a new model for the interactive effects is presented. Complex codiffusion behavior of As and P is presented and modeling concepts elucidated. Tradeoffs such as sheet resistance for a given junction depth, and how these depend on impurities, as well as soak vs. spike rapid thermal anneals (RTA), can be understood with simulation models.

Physical Modeling of Layout-Dependent Transistor Performance

Design for Manufacturability (DFM) is a phrase that often accompanies discussion of layout optimization for lithography process effects, particularly Optical Proximity Correction (OPC). In an environment where process technology and circuit design are developed together, many other process-layout co-optimization strategies can be investigated. In this paper we discuss physical modeling to enable co-optimization strategies from a device performance point of view by examining layout-induced variation in front-end manufacturing processes used to engineer transistor strain and dopant diffusion/activation.