Patrick Pai

A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels

A front-end IC for EPR-IV partial-response maximum likelihood (PRML) detection systems used in magnetic recording systems is developed. Reorganization of the front-end architecture reduces clock acquisition time and lowers chip complexity and power. A new six-pole 80-MHz continuous-time filter equalizes waveforms to the desired ERR-IV target. The equalizer is tuned in quality-factor and frequency to a synthesized system clock, reducing drifts due to processing and temperature variations. An on-chip timing recovery circuit, incorporating a 160-MHz sampled-analog phase detector and 200-MHz voltage-controlled oscillator (VCO) regenerates the data clock. The phase detector used is appropriate for (1, 7) code, and can be extended to operate on (0, k) codes. During head seeks, a secondary loop incorporating the VCO locks to the write clock and acquires the anticipated read-clock frequency. All signal paths are serial and fully differential. The chip is fabricated in a 1-/spl mu/m CMOS process.

A 40-mW 55 Mb/s CMOS equalizer for use in magnetic storage read channels

A monolithic active equalizer in 2-/spl mu/m CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional 7-pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations. >

A single-chip universal digital satellite receiver with 480 MHz IF input

A complete single-chip universal digital satellite receiver supports all current DBS system standards. The mixed signal device accepts a modulated data stream at up to 90 Mb/s and delivers a demodulated error-corrected output data stream. The IC features an analog front-end with 480 MHz IF downconversion and dual 8 bit A/D converters, an all-digital BPSK/QPSK/OQPSK receiver, and a DVB/DSS/DigiCipher-II compliant concatenated Viterbi/Reed-Solomon FEC decoder with on-chip deinterleaver RAM. All required clocks are generated on chip from a single reference crystal. The chip contains 1.2 M transistors in a 22 mm/sup 2/ die in single-poly 0.35 /spl mu/m CMOS with four layers of metal.

Analog front-end architectures for high-speed PRML magnetic read channels

IC front-end architectures for a CMOS partial-response maximum likelihood magnetic read channel are re-examined. By organizing the front-end system components properly, several properties may be optimized; clock-recovery acquisition time can be minimized, sensitivity to ADC quantization noise may be reduced, and overall power and complexity may be minimized. Channel simulation reveals that efficient equalization may be carried out with an adaptive, continuous-time equalizer with only 4-poles, which increases drive packing densities over conventionally equalized channels. 1-/spl mu/m CMOS circuits necessary for realization of the desired 200 MHz front-end are designed, partially realized, and tested. >

A simple continuous-time equalizer for use in magnetic storage read channels

A four-pole continuous-time equalizer has been developed to minimize the error rate in rigid-disk magnetic storage channels employing peak detection at high recording densities. The design process consisted of two parts. A nominal model of the disk drive characteristics in the time and frequency domains was obtained from digitized waveforms at the output of a read-head amplifier in a disk drive system. The relative performance of candidate equalizers was studied by subjecting them to the measured data waveforms and then either estimating or measuring the resulting bit error rate in a simulated peak detector, operating on the equalized waveforms. The equalizer outperforms more complex structures proposed for this task and is well suited for implementation as an analog CMOS active filter with low power dissipation. Its constellation of four poles and a zero appears to be useful for several types of magnetic media. >

A simple L-C equalizer for use in magnetic storage read channels

A fourth order continuous-time equalizer has been developed to minimize the error rate in magnetic storage channels with high recording densities. The equalizer outperforms more complex structures proposed for this task, and is well suited for implementation as an analog CMOS active filter with low power dissipation. A numerical design procedure for the filter is described.<<ETX>>