James Yingbo Jia

A Novel 65 nm Radiation Tolerant Flash Configuration Cell Used in RTG4 Field Programmable Gate Array

The newly introduced radiation-tolerant flash-based FPGA, RTG4, uses a novel configuration cell design composed of a NMOS switch controlled by a totem pole p-channel flash and n-channel flash construction. Its radiation tolerance is far superior to that in the present available Flash-based FPGA. This paper describes the radiation hardening by design (RHBD) process for the new flash-based configuration cell. A subtle and unique retention issue was found and resolved through studying physical mechanisms and conducting experiments.

Combine Flash-Based FPGA TID and Long-Term Retention Reliabilities Through

Reliability test results of data retention and total ionizing dose (TID) in 65 nm Flash-based field programmable gate array (FPGA) are presented. Long-chain inverter design is recommended for reliability evaluation because it is the worst case design for both effects. Based on preliminary test data, both issues are unified and modeled by one natural decay equation. The relative contributions of TID induced threshold-voltage shift and retention mechanisms are evaluated by analyzing test data.

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Reliability test results of data retention and total ionizing dose (TID) in 65 nm Flash-based field programmable gate array (FPGA) are reviewed. Long-chain inverter design is recommended for reliability evaluation because it can detect degradations of both programmable and erased Flash cells. All the reliability issues are unified and modeled by one natural decay equation.

Shift

We present a study on NBTI life time for high voltage PMOS transistors. These devices are used in erasing and programming control circuits for a floating-gate flash based FPGA array fabricated with a 65nm embedded process. NBTI stress tests were performed with different gate biases and at different temperatures. Life time model parameters, such as voltage acceleration factor and activation energy, were obtained from the tested results. NBTI device life time was assessed against product requirements. A 50 times (50X) margin in life time was estimated for our baseline process, based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or completely depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases. To further improve NBTI lifetime margin against product requirement, LDD doping was increased and optimized. We are able to further improve HV PMOS device performance in this regard.

Flash-Based FPGA TID and Long-Term Retention Reliability through VT Shift Investigation

In this work, HCI effect of PMOS FETs was studied. For a given drain bias, electron trapping is the dominant degradation mechanism for a gate bias close to 20% of the drain bias. A maximum gate current is seen under this bias condition. Hole trapping is dominant when the gate bias is equal to the drain bias where drain current is the maximum. Electron trapping enhances PMOS driving current or Idsat whereas hole trapping degrades Idsat. The effect of electron trapping and hole trapping cancel each other. As a result, life time is longer when two trapping mechanisms are involved compared with the life time with one trapping mechanism. In this study, device Idsat degradation was measured with different gate and drain biases in a DC mode. An AC stress is also performed in which gate/drain bias waveforms follow those of a typical switching inverter. Due to the above-mentioned cancelling effect, PMOS HCI AC life time is longer and the DC to AC conversion factor is much larger than conventionally used values. The effect of STI stress on HCI degradation is briefly studied. Layouts to minimize this effect are then proposed.

NBTI life time of a high voltage PMOS FET

We present a study on NBTI induced device degradation and mechanism for a high voltage PMOS FET. This device is used in erasing and programming a floating-gate Flash based FPGA array fabricated with a 65nm embedded process. NBTI induced device degradation has attracted a lot of attention and becomes the major limitation of logic PMOS reliability. Unlike logic devices which operate at high frequencies, program and erase of Flash cells are operated at a much lower frequency. Erase time is typically a few seconds per cycle, thus, in our study NBTI stress is done in a DC mode or a slow AC mode. In this case some device degradation gets recovered and a longer life time has been seen than logic applications. We have performed NBTI stress tests with different biases and at different temperatures. Life time model parameters, for example, voltage acceleration factor and Ea were obtained from the tested data. NBTI device life time was derived for erase conditions. A 50 times margin in life time was seen for our baseline process based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or wholly depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases.

Voltage dependence and AC life time of PMOS HCI

We present studies of an extrinsic program disturb mechanism in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. It is concluded that multiple positive charges are involved during disturb to explain the observed extrinsic behavior. Its failure rate was improved with tunnel oxidation process tuning and stronger pre-oxidation cleans.

High voltage PMOS FET NBTI results and mechanism

We present a highly reliable Flash based FPGA fabricated with a 65nm embedded process. A very robust ON and OFF Vt window, over 8V, has been achieved with tight cell to cell distributions. 1k program/erase cycles have been performed and charge trap induced Vt window loss is less than 0.2V. Some initial Vt shift is seen at erase side after retention bake. The shift saturates after 24 hours and the post-bake Vt window is close to 8V. There is still a 2V margin from our design spec which is 6V. Operation disturb life time was extrapolated from an accelerated test. AC life time is greater than 2000 years. For some high security applications we provide a user-verify feature. Based on accelerated testing we have proposed the number of user verifies and predicted the error rate.

Program disturbs and process optimization in a 65 nm Flash FPGA

We present a study of the disturb mechanism encountered in a novel user verify technique that can be used to enhance the security of a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. Two disturb mechanisms are studied in detail. The intrinsic disturb mode is related to Fowler-Nordheim (FN) tunneling, whereas an extrinsic disturb mode involves traps which enhance the tunneling probability. The effect of single and multiple positive charges is simulated. It is concluded that multiple charges are involved during disturb to explain the observed extrinsic behavior. Accelerated testing predicts that 10k verify operations can be performed with an error rate less than 1ppm for a five million gate FPGA, equivalent to a FIT rate of approx. 0.001 failures per 109 hours per million gates when applied over a 20 year lifetime. The low verify-induced error rate makes the technique suitable for enhancing security by providing timely detection of malicious tampering attacks.

Performance and reliability of a 65nm Flash based FPGA

We present a study of cycling induced degradation of a two transistor Flash memory cell with a shared floating gate. The cell directly serves as a configurable interconnection switch in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. By optimizing the poly re-oxidation, LDD implant and spacer module, the cell endurance is significantly improved at both the single cell and 1 Mbit test-array levels.