Paul Lettieri

A quad-band GSM/GPRS/EDGE SoC in 65nm CMOS

A quad-band 2.5G SoC integrates all the RF, DSP, ARM, audio and other baseband processing functions into a single 65nm CMOS die. The radio draws a battery current of 49mA in the RX-mode, and 86mA in the GMSK TX-mode. The low-IF receiver achieves a sensitivity of −110dBm at the antenna, corresponding to a noise figure of 2.4dB at the device input. The 8PSK ±400kHz modulation mask is −64.1/62.7dBc for high/low bands, with an RMS EVM of 2.45/1.95%.

A Single-Chip Bluetooth EDR Device in 0.13μm CMOS

A low-power single-chip Bluetooth EDR device is realized using a configurable transformer-based RF front-end, a low-IF receiver and direct-conversion transmitter architecture. It is implemented in a 0.13mum CMOS process and occupies 11.8mm2. Sensitivity for 1, 2 and 3Mb/s rates is -88, -90, and -84dBm and transmitter differential EVM is 5.5% rms.

A Quad-Band GSM/GPRS/EDGE SoC in 65 nm CMOS

A quad-band 2.5G SoC integrating all the RF, DSP, ARM, audio and other baseband processing functions into a single 65 nm CMOS die is described. The paper focuses on the radio portion mostly, and addresses the challenges of realizing a complete GSM/EDGE SoC with the RF integrated along with the rest of digital baseband circuitry. Several circuit level as well as architectural techniques are presented to realize a very low-cost and low-power 2.5G radio while meeting the stringent cellular requirements with wide margin. The radio draws a battery current of 49 mA in the receiver-mode, and 86/77 mA in the GMSK/8PSK transmit-mode. The low-IF receiver achieves a sensitivity of -110 dBm at the antenna, corresponding to a noise figure of 2.4 dB at the device input. The 8PSK±400 kHz modulation mask is - 64.1/62.7 dBc for high/low bands, with an RMS EVM of 2.45/1.95%. The radio core area is 3.95 mm2 .

A Fully Integrated Quad-Band GPRS/EDGE Radio in 0.13μm CMOS

This radio integrates all the receive and transmit functions required to support a quad-band GSM/GPRS/EDGE application into a single CMOS chip. Compared to the published work, this transceiver is implemented in low-cost digital 0.13 mum CMOS, achieves a superior receive and transmit performance, and yet has up to 2x lower receive power consumption, a key requirement in cellular applications.

Active base stations and nodes for wireless networks

Mobile and wireless network systems are characterized by a highly time varying and heterogeneous operational environment. For example, the wireless link bandwidth and bit error rate can change due to fading, mobile nodes may have different capabilities, and in the course of its movements a mobile node may visit base stations that provide different sets of services, protocols, and interfaces. Adaptability, in various forms and at various levels of the system, is a key to combating the inherent variability of a mobile environment. This paper describes our work on Active Base Stations and Active Mobile Nodes that use the general approach of active networking to allow run-time application-specific customization of communication processing done on packets at the base station and the mobile end-nodes. This is accomplished by a software-hardware architecture that allows application specified reconfigurable hardware datapaths as well as software functions to be inserted in the path of specified packet flows at the base station and the end-node. The reconfigurable hardware datapaths as well as software functions, called Packet Processing Filters (PPF), can be uploaded or downloaded across the network, and their behavior controlled via parameter adaptation. Examples of adaptive capabilities enabled by Active Base Stations and Active Wireless Nodes include: (i) flow-specific adaptation of coding/decoding and packet lengths at the two ends of a time varying wireless link; (ii) adaptation of encryption/decryption on the wireless link according to changing locale and security environment; (iii) downloading a new or proprietary MAC protocol from a base station to visiting foreign mobiles; and (iv) dynamically uploading mobile specified services to a base station of a different service provider. We present the basic architecture and implementation approach of our system, and description of the initial software/hardware prototype.

Transmitter development for cellular integrated circuits

This article reviews transmitter topologies for radio transceivers with emphasis on cellular applications. In the first section it discusses different architectures and the challenges in practical implementations. Then it presents a transmitter as part of a fully integrated transceiver for GSM/GPRS/EDGE.

A fully integrated SoC for 802.11b in 0.18 /spl mu/m CMOS

A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-/spl mu/m CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range.