Pen-Li Huang

A release-on-demand wireless CMOS drug delivery SoC based on electrothermal activation technique

Recently, micro- and nano-technologies have enabled rapid progress in biomedical applications. Although in vitro analytical and diagnostic tools have been the focus of such technologies, in vivo therapeutic and sensing applications have received significant attention in the past few years. Novel implantable drug delivery devices, which can precisely control key therapy parameters, have the potential to increase the efficacy of drug therapy [1]. This paper presents an implantable CMOS drug delivery SoC, in which a wireless controller/actuation circuitry and a drug delivery array are monolithically integrated. Compared with current technologies, the advantages of the proposed device include lower system cost, smaller device size and lower power consumption. This device can be implanted by minimally invasive surgery and is suitable for the localized diagnosis/therapy of cancers, or the immediate treatment of unpredictable heart attacks [2] by releasing drugs such as nonapeptide leuprolide acetate or nitroglycerin. Physicians can also make non-invasive therapy modification by using the wireless capability.

A Controlled-Release Drug Delivery System on a Chip Using Electrolysis

A system-on-a-chip (SOC) with integrated drug reservoirs for drug delivery is proposed. Electrolysis is used to generate microbubbles, which are employed as a force to open the reservoirs and release the drug. Wireless components, including an on/off keying receiver, microcontrol unit, regulator, clock divider, and power-on reset, are integrated for remote drug activation. The proposed microchip is fabricated by Taiwan Semiconductor Manufacturing Company 0.35-μm CMOS technology followed by post-IC processing. The total size is 2.48 mm2, and the power consumption is 7.57 mW. The in vitro experiment has proven the feasibility of the proposed drug delivery SOC.

Ultralow-Loss and Broadband Micromachined Transmission Line Inductors for 30–60 GHz CMOS RFIC Applications

In this paper, for the first time, we demonstrate that ultralow-loss and broadband transmission line (TL) inductors can be obtained by using the CMOS-process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the TL inductors. The results show that a 112.8% (from 14.37 to 30.58) and a 201.1% (from 6.33 to 19.06) increase in Q-factor, a 9.7% (from 0.91 to 0.998) and a 28.3% (from 0.778 to 0.998) increase in maximum available power gain GAmax, and a 0.404-dB (from 0.412 to 7.6times10-3 dB) and a 1.082-dB (from 1.09 to 8.4times10-3 dB) reduction in minimum noise figure NFmin were achieved at 30 and 60 GHz, respectively, for a 162.2 pH TL inductor after the backside ICP dry etching. The state-of-the-art performances of the on-chip TL inductors-on-air suggest that they are very suitable for application to realize ultralow-noise 30-60-GHz CMOS radio-frequency integrated circuit. In addition, the CMOS-process compatible backside ICP etching technique is very promising for system-on-a-chip applications.

A 4.9-dB NF 53.5–62-GHz micro-machined CMOS wideband LNA with small group-delay-variation

A 53.5–62-GHz wideband CMOS low-noise amplifier (LNA) with excellent phase linearity property is reported. Current-sharing technique is adopted to reduce power dissipation. The LNA (STD LNA) consumed 29.1 mW and achieved input return loss (S11) of −10.3∼ −19.5 dB, output return loss (S 22 ) of −13.8∼ −27.8 dB, forward gain (S 21 ) of 8.1∼ 11.1 dB, and reverse isolation (S 12 ) of −49.9∼ −60.2 dB over the 53.5–62-GHz-band. The minimum NF (NF min ) is 5.4 dB at 62 GHz. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to remove the silicon underneath the LNA. After the ICP etching, the LNA (ICP LNA) achieved maximum S 21 (S 21-max ) of 13.2 dB, 2.1 dB higher than that (11.1 dB) of the STD LNA. In addition, the ICP LNA achieved NF min of 4.9 dB, 0.5 dB lower than that (5.4 dB) of the STD LNA. These results demonstrate the proposed LNA architecture in conjunction with the backside ICP technology is very promising for 60-GHz-band RFIC applications.

An Implantable Release-on-Demand CMOS Drug Delivery SoC Using Electrothermal Activation Technique

An implantable system-on-a-chip (SoC) integrating controller/actuation circuitry and 8 individually addressable drug reservoirs is proposed for on-demand drug delivery. It is implemented by standard 0.35-μm CMOS technology and post-IC processing. The post-IC processing includes deposition of metallic membranes (200Å Pt/3000Å Ti/200Å Pt) to cap the drug reservoirs, deep dry etching to carve drug reservoirs in silicon as drug containers, and PDMS layer bonding to enlarge the drug storage. Based on electrothermal activation technique, drug releases can be precisely controlled by wireless signals. The wireless controller/actuation circuits including on-off keying (OOK) receiver, microcontroller unit, clock generator, power-on-reset circuit, and switch array are integrated on the same chip, providing patients the ability of remote drug activation and noninvasive therapy modification. Implanted by minimally invasive surgery, this SoC can be used for the precise drug dosing of localized treatment, such as the cancer therapy, or the immediate medication to some emergent diseases, such as heart attack. In vitro experimental results show that the reservoir content can be released successfully through the rupture of the membrane which is appointed by received wireless commands.

A Novel Coplanar-Waveguide Band-Pass Filter Utilizing the Inductor–Capacitor Structure in 0.18 µm Complementary Metal–Oxide–Semiconductor Technology for Millimeter-Wave Applications

A low-insertion-loss V-band complementary metal–oxide–semiconductor (CMOS) band-pass filter is demonstrated. The proposed filter architecture has the following features: the low-frequency transmission-zero (ωz1) and the high-frequency transmission-zero (ωz2) can be tuned individually by adjusting the value of the series capacitor (Cs) and the size of the built-in inductor–capacitor (LC) resonator, respectively. The folded short-stub technique is used to reduce the chip size of the filter. To reduce the silicon substrate loss, the CMOS-process-compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter. After the ICP etching, the filter achieves insertion-loss (1/S21) lower than 3 dB over the frequency range of 46.5–85.5 GHz. The minimum insertion-loss is -1.8 dB at 60 GHz.

Ultra-Low-Loss and Broadband Micromachined Inductors and Transformers for 30-100 GHz CMOS RFIC Applications by CMOS-Compatible ICP Deep Trench Technology

A CMOS-compatible backside inductively-coupled-plasma (ICP) deep trench technology has been developed to enhance the performances of RF monolithic inductors and transformers for 30-100 GHz CMOS RFIC applications. The results show that an 112.8% (from 14.37 to 30.58) and a 201.1% (from 6.33 to 19.06) increase in Q-factor, a 9.7% (from 0.91 to 0.998) and a 28.3% (from 0.778 to 0.998) increase in maximum available power gain (GAmax), and a 0.404 dB (from 0.412 dB to 7.6times10-3 dB) and a 1.082 dB (from 1.09 dB to 8.4times10-3 dB) reduction in minimum noise figure (NFmin) were achieved at 30 GHz and 60 GHz, respectively, for a 162.2 pH TL inductor after the backside ICP dry etching. In addition, we demonstrate that high-coupling and ultra-low-loss 30-100 GHz transformers can be achieved by using single-turn two-layer interlaced stacked (STIS) structure implemented in a standard CMOS technology. Significant improvements in Q-factor (from 5.04 to 29.8 at 70 GHz) and G Amax (from 0.885 to 0.984 at 70 GHz) were achieved for the STIS transformers after the ICP etching. Besides, the ICP technology is also capable of improving the isolation between RF/analog and digital circuits and thus paves a way for SOC