Chang-Zhi Chen

Analysis and Design of a CMOS UWB LNA With Dual-

A wideband low-noise amplifier (LNA) based on the current-reused cascade configuration is proposed. The wideband input-impedance matching was achieved by taking advantage of the resistive shunt-shunt feedback in conjunction with a parallel LC load to make the input network equivalent to two parallel RLC-branches, i.e., a second-order wideband bandpass filter. Besides, both the inductive series- and shunt-peaking techniques are used for bandwidth extension. Theoretical analysis shows that both the frequency response of input matching and noise figure (NF) can be described by second-order functions with quality factors as parameters. The CMOS ultra-wideband LNA dissipates 10.34-mW power and achieves S 11 below -8.6 dB, S 22 below -10 dB, S 12 below -26 dB, flat S 21 of 12.26 ± 0.63 dB, and flat NF of 4.24 ± 0.5 dB over the 3.1-10.6-GHz band of interest. Besides, good phase linearity property (group-delay variation is only ±22 ps across the whole band) is also achieved. The analytical, simulated, and measured results agree well with one another.

RLC

A 3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only plusmn17.4 ps across the whole band) using standard 0.18 mum CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 22.7 mW power and achieves input return loss (S22) of -9.7 ~ -19.9 dB, output return loss (S22) of -8.4 ~ -22.5 dB, flat forward gain (S22) of 11.4 plusmn 0.4 dB, reverse isolation (S12) of 40 ~ -48 dB, and noise figure (NF) of 4.12 ~ 5.16 dB over the 3.1-10.6 GHz band of interest. Good 1-dB compression point (P1dB) of -7.86 dBm and input third-order inter-modulation point (IIP3) of 0.72 dBm are achieved at 6.4 GHz. The chip area is only 681 mum times 657 mum excluding the test pads.

-Branch Wideband Input Matching Network

In this brief, we demonstrate that high-quality-factor and low-power-loss transformers can be obtained if the optimized pattern ground shields (OPGS) of polysilicon is adopted and the CMOS process-compatible backside inductively coupled-plasma (ICP) deep-trench technology is used to selectively remove the silicon underneath the transformers completely. OPGS means that the redundant PGS of a traditional complete PGS, which is right below the spiral metal lines of the transformer, is removed for the purpose of reducing the large parasitic capacitance. The results show that, if the OPGS was adopted and the backside ICP etching was done, a 69.3% and a 253.6% increase in quality factor, a 10.5% and a 14% increase in magnetic-coupling factor (kIm), a 17.2% and a 51.1% increase in maximum available power gain (GAmax), and a 0.682- and a 1.79-dB reduction in minimum noise factor (NFmin) were achieved at 5 and 8 GHz, respectively, for a bifilar transformer with an overall dimension of 230times215 mum2

An Excellent Phase-Linearity 3.1-10.6 GHz CMOS UWB LNA Using Standard 0.18 μm CMOS Technology

In this paper, we demonstrate that the noise figure (NF) of a P+ active-area (AA) mesh inductor is much better than that of its standard version. In a P+AA mesh inductor, the AA with P+ implantation is added beneath it in the shape of a mesh to reduce its capacitive and magnetic coupling with the silicon substrate. Two 3.1-10.6-GHz CMOS ultrawideband (UWB) low-noise amplifiers (LNAs), one with P+ AA mesh inductors (AA mesh UWB LNA) and the other with standard inductors (STD UWB LNA), are implemented to study the effect of the P+ AA mesh on their performances. The results show that a 0.62-dB improvement in NF (from 0.8 to 0.18 dB) was achieved at 10.5 GHz for the input inductor LG1 if the P+ AA mesh had been added beneath it. In addition, the AA mesh UWB LNA achieved a low and flat NF of 3.365 plusmn 0.225 dB over the band of interest, notably better than that (4.64 plusmn 0.52 dB) of the STD UWB LNA.

A High-Performance Micromachined RF Monolithic Transformer With Optimized Pattern Ground Shields (OPGS) for UWB RFIC Applications

A low-power low-phase-noise 48-GHz CMOS LC voltage-control oscillator (VCO) and a low-power 60-GHz CMOS low-noise amplifier (LNA) for 60-GHz dual-conversion receiver are reported. The VCO dissipated 5.556 mW power, and achieved state-of-the-art phase noise of −105 dBc/Hz at 1-MHz offset from 47.84 GHz. The corresponding figure-of-merit (FOM) was −191.1 dBc/Hz, which is better than those of the reported CMOS LC VCOs around 48 GHz in the literature. Besides, the LNA consumed 21.4 mW power, and achieved input return loss (S<inf>11</inf>) of −10.6∼ −37.4 dB, voltage gain (A<inf>V</inf>) of 10.7∼ 18.8 dB, reverse isolation (S<inf>12</inf>) of −43.5∼ −48.1 dB, input referred 1-dB compression point (P<inf>1dB-in</inf>) of −16.2∼ −20.8 dBm, and input third-order inter-modulation point (IIP3) of −4∼ −7.5 dBm over the 57-64-GHz-band of interest.

Low Noise-Figure

In this paper, we demonstrate that high-coupling and ultra-low-loss transformers for 60-100 GHz CMOS RFIC applications can be achieved by using single-turn two-layer interlaced stacked (STIS) structure implemented in a standard CMOS technology. State-of-the-art G Amax of 0.711, 0.922, and ~1 (i.e. NFmin of 1.48, 0.35, and ~0 dB) were achieved at 60, 80, and 100 GHz, respectively, for a STIS transformer with an inner dimension of 50times50 mu2 and a metal width of 5 mum, mainly due to the high magnetic-coupling factor (klm) and the high resistive-coupling factor (kRe). In addition, a 94.1% (from 5.61 to 10.89) and a 196.8% (from 8.36 to 24.81) increase in Q-factor, a 14.2% (from 0.711 to 0.812) and a 8.5% (from 0.922 to ~1) increase in G Amax, and a 0.58 dB (from 1.48 dB to 0.90 dB) and a 0.35 dB (from 0.35 dB to ~0 dB) decrease in NFmin were achieved at 60 and 80 GHz, respectively, for the transformer after the post-process of proton implantation. The present analysis is helpful for RF engineers to design ultra-low-voltage high-performance 60-100 GHz transformer-feedback CMOS (or BiCMOS) LNAs and VCOs, and other RF-ICs which include transformers

{\rm P}^{+}

A low-power and wide-locking-range 55.8-GHz (V-band) injection-locked frequency-divider (ILFD) using standard 0.13 μm CMOS technology is reported. To enhance locking range, a shunt inductor was introduced in the source node of the cross-coupled pair to maximize the equivalent load impedance of the tail transistor, i.e. to maximize the internal power, over the frequency band of interest. In addition, the inductors and capacitors of the LC-tank were implemented by low-Q micro-stripline inductors and high-Q varactors, respectively, to further improve the locking range of the ILFD. The result shows that a wide-locking-range of 7.1 GHz (from 48.7 GHz to 55.8 GHz, 13.6%) was achieved. The power consumption of the ILFD is only 2 mW from a 1.1 V power supply. The chip area was only 0.66×0.48 mm2 excluding the test pads.

AA Mesh Inductors for CMOS UWB RFIC Applications

A 58-GHz (V-band) CMOS direct injection-locked frequency-divider (DILFD) using input-power-matching technique for locking-range enhancement is reported for the first time. In an input-power-matching technique, an inductive input-matching-network is added to the gate of the NMOS switch to optimize the input-power-matching, i.e. to maximize the internal power, over the frequency band of interest. This DILFD architecture also features a very low input capacitance; therefore, high operating frequency of 58.2 GHz can be achieved. The DILFD dissipated 8.45 mW power from a 1.3 V power supply, and achieved a total locking range of 9.3 GHz (48.9–58.2 GHz; 17.4%), which is 400% higher than that (1.86 GHz (3%)) of a traditional DILFD without the input-matching-network for comparison. The chip area was only 0.585×0.492 mm2 excluding the test pads.

Low-power 48-GHz CMOS VCO and 60-GHz CMOS LNA for 60-GHz dual-conversion receiver

We demonstrate that miniature millimeter-wave (MMW) band-pass filter can be obtained by replacing the traditional eoplanar waveguide structures with the miniature lumped-spiral inductors and metal-insulator-metal (MIM) capacitors. To study the substrate effects on the performances of the spiral inductor and filter, CMOS-compatible backside inductively-coupled-plasma (ICP) deep trench technology was used to selectively remove the silicon underneath them. The results show that a 70.9% (from 5.8 to 9.91) and a 298.7% (from 2.33 to 9.29) increase in Q-factor were achieved at 40 GHz and 60 GHz, respectively, for a 251.7 pH inductor after the ICP etching. In addition, a 0.9 dB (from -5.4 dB to -4.6 dB) improvement in peak insertion loss (S23) was achieved for the miniature bandpass filter with 3-dB bandwidth of 47.7 GHz (18.4 ~ 66.1 GHz) after the ICP etching. The chip area of the miniature filter was only 206 mum x 106 mum excluding the test pads.

High-Coupling and Ultra-Low-Loss Interlaced Stacked Transformers for 60-100 GHz CMOS RFIC Applications

In this paper, we demonstrate that miniature millimeter-wave band-pass filter can be obtained by replacing the traditional coplanar waveguide structures with the miniature lumped-spiral inductors and metal–insulator–metal (MIM) capacitors. To study the silicon substrate effects on the performances of the miniature spiral inductor and band-pass filter, complementary metal–oxide–semiconductor (CMOS)-process-compatible backside inductively-coupled-plasma (ICP) deep-trench technology was used to selectively remove the silicon underneath them. The results show that a 70.9% (from 5.8 to 9.91) and a 298.7% (from 2.33 to 9.29) increase in Q-factor were achieved at 40 and 60 GHz, respectively, for a 251.7 pH miniature spiral inductor after the backside ICP dry etching. In addition, a 0.9 dB (from -5.4 to -4.6 dB) improvement in peak insertion loss (S21) was achieved for a miniature band-pass filter with 3-dB bandwidth of 47.7 GHz (18.4–66.1 GHz) after the backside ICP dry etching. The chip area of the miniature band-pass filter was only 206×106 µm2 excluding the test pads.