Yo-Sheng Lin

A 2.17-dB NF 5-GHz-band monolithic CMOS LNA with 10-mW DC power consumption

The state-of-the-art noise figures of 2.17 dB and 3.0 dB at 5 GHz band from monolithic CMOS LNAs with 10 mW dissipation on thin (/spl sim/ 20 /spl mu/m) and normal (750 /spl mu/m) substrates are presented. Excellent Input return loss (S/sub 11/) of -45 dB, high P/sub 1dB/ of -8.3 dBm and large IIP3 of 0.3 dBm were also obtained. The excellent performance of the LNAs is attributed to the methodology we developed.

Micromachined CMOS LNA and VCO by CMOS-compatible ICP deep trench technology

Selective removal of the silicon underneath the inductors in RF integrated circuits based on inductively coupled plasma (ICP) deep trench technology is demonstrated by a complementary metal-oxide-semiconductor (CMOS) 5-GHz low-noise amplifier (LNA) and a 4-GHz voltage-controlled oscillator (VCO). Design principles of a multistandard LNA with flat and low noise figures (NFs) within a specific frequency range are also presented. A 2-dB increase in peak gain (from 21 to 23 dB) and a 0.5-dB (from 2.28 to 1.78 dB) decrease in minimum NF are achieved in the LNA while a 3-dB suppression of phase noise is obtained in the VCO after the ICP backside dry etching. These results show that the CMOS-process-compatible backside ICP etching technique is very promising for system-on-a-chip applications.

Analysis and Design of a CMOS UWB LNA With Dual-

A wideband low-noise amplifier (LNA) based on the current-reused cascade configuration is proposed. The wideband input-impedance matching was achieved by taking advantage of the resistive shunt-shunt feedback in conjunction with a parallel LC load to make the input network equivalent to two parallel RLC-branches, i.e., a second-order wideband bandpass filter. Besides, both the inductive series- and shunt-peaking techniques are used for bandwidth extension. Theoretical analysis shows that both the frequency response of input matching and noise figure (NF) can be described by second-order functions with quality factors as parameters. The CMOS ultra-wideband LNA dissipates 10.34-mW power and achieves S 11 below -8.6 dB, S 22 below -10 dB, S 12 below -26 dB, flat S 21 of 12.26 ± 0.63 dB, and flat NF of 4.24 ± 0.5 dB over the 3.1-10.6-GHz band of interest. Besides, good phase linearity property (group-delay variation is only ±22 ps across the whole band) is also achieved. The analytical, simulated, and measured results agree well with one another.

RLC

In this paper, we demonstrate the effects of CMOS technology scaling on the high temperature characteristics (from 25/spl deg/C to 125/spl deg/C) of the four components of off-state drain leakage (I/sub off/) (i.e. subthreshold leakage (I/sub sub/), gate edge-direct-tunneling leakage (I/sub EDT/), gate-induced drain-leakage (I/sub GIDL/), and bulk band-to-band-tunneling leakage (I/sub B-BTBT/)). In addition, the high temperature characteristics of I/sub off/ with reverse body bias (V/sub B/) for the further reduction of the standby leakage are also demonstrated. The discussion is based on the data measured from three CMOS logic technologies (i.e., low-voltage and high performance (LV), low-power (LP), and ultra-low-power (ULP)) and three generations (0.18 /spl mu/m, 0.15 /spl mu/m, and 0.13 /spl mu/m). Experiments show that the optimum V/sub B/, which minimizes I/sub off/, is a function of temperature. The experiments also show that for CMOS logic technologies of the next generations, it is important to control I/sub B-BTBT/ and I/sub GIDL/ by reducing effective doping concentration and doping gradient. It seems that in order to conform on-state gate leakage (I/sub G-on/) and I/sub EDT/ specifications and to retain a 10-20% performance improvement at the same time, it is indispensable to use high-quality and high-dielectric-constant materials to reduce effective oxide thickness (EOT). The role of each leakage component in SRAM standby current (I/sub SB/) is also analyzed.

-Branch Wideband Input Matching Network

This paper presents a wideband low-noise amplifier (LNA) based on the cascode configuration with resistive feedback. Wideband input-impedance matching was achieved using a shunt-shunt feedback resistor in conjunction with a preceding π -match network, while the wideband gain response was obtained using a post-cascode inductor (LP), which was inserted between the output of the cascoding transistor and the input of the shunt-shunt resistive feedback network to enhance the gain and suppress noise. Theoretical analysis shows that the frequency response of the power gain, as well as the noise figure (NF), can be described by second-order functions with quality factors or damping ratios as parameters. Implemented in 90-nm CMOS technology, the die area of this wideband LNA is only 0.139 mm2 including testing pads. It dissipates 21.6-mW power and achieves S11 below -10 dB, S22 below -10 dB, flat S21 of 9.6 ±1.1 dB, and flat NF of 3.68 ± 0.72 dB over the 1.6-28-GHz band. Besides, excellent input third-order inter-modulation point of +4 dBm is also achieved. The analytical, simulated, and measured results are mutually consistent.

Leakage scaling in deep submicron CMOS for SoC

In this paper, we demonstrate an SiGe HBT ultra-wideband (UWB) low-noise amplifier (LNA), achieved by a newly proposed methodology, which takes advantage of the Miller effect for UWB input impedance matching and the inductive shunt-shunt feedback technique for bandwidth extension by pole-zero cancellation. The SiGe UWB LNA dissipates 25.8-mW power and achieves S11 below -10 dB for frequencies from 3 to 14 GHz (except for a small range from 10 to 11 GHz, which is below -9 dB), flat S21 of 24.6 plusmn 1.5 dB for frequencies from 3 to 11.6 GHz, noise figure of 2.5 and 5.8 dB at 3 and 10 GHz, respectively, and good phase linearity property (group-delay variation is only plusmn28 ps across the entire band). The measured 1-dB compression point (P1 dB) and input third-order intermodulation point are -25.5 and -17 dBm, respectively, at 5.4 GHz.

Analysis and Design of a 1.6–28-GHz Compact Wideband LNA in 90-nm CMOS Using a

A low-voltage (0.5 V) and low-power (4.535 mW) monolithic biomedical system-on-a-chip (SOC) consisting of a receiver, a transmitter, a microcontrol unit, and an analog-to-digital converter (ADC), implemented in a 0.18-μm CMOS technology for intrabody communication is first reported. The SOC can take command through a human body and activate (or turn on) the ADC and transmitter inside the SOC. Then, a biomedical signal is converted to digital format and transmitted to the RF gateway through a human body. With this transmission methodology and the proposed SOC circuit, it is much more power efficient than wireless communication. Moreover, since no antenna is required, the chip size of the SOC is only 1.5 mm2, excluding the test pads.

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A quick wireless label-free detection of disease-related C-reactive proteins (CRPs) using a 200-mum-long microelectromechanical systems (MEMS) microcantilever housed in a 7times7 mm2 reaction chamber with a safe reusable feature is reported. The assay time ranges from about 30 min to 3 h, depending on accuracy. The deflection of the microcantilever due to specific CRP-antiCRP binding is detected using a position-sensitive detector. The converted bio-signal is transmitted by a custom designed wireless amplitude-shift-keying (ASK) transceiver IC fabricated in a 0.18 mum CMOS process. CRP concentrations from 1 mug/mL to 500 mug/mL can be detected. A 0.2-Hz 1-V ac signal instead of traditional bases/acids is applied to the bio-MEMS sensor to unbind the CRP from the microcantilever for reusability.

-Match Input Network

Ga/sub 0.51/In/sub 0.49/P/In/sub 0.15/Ga/sub 0.85/As/GaAs pseudomorphic doped-channel FETs exhibiting excellent DC and microwave characteristics were successfully fabricated. A high peak transconductance of 350 mS/mm, a high gate-drain breakdown voltage of 31 V and a high maximum current density (575 mA/mm) were achieved. These results demonstrate that high transconductance and high breakdown voltage could be attained by using In/sub 0.15/Ga/sub 0.85/As and Ga/sub 0.51/In/sub 0.49/P as the channel and insulator materials, respectively. We also measured a high-current gain cut-off frequency f/sub t/ of 23.3 GHz and a high maximum oscillation frequency f/sub max/ of 50.8 GHz for a 1-/spl mu/m gate length device at 300 K. RF values where higher than those of other works of InGaAs channel pseudomorphic doped-channel FETs (DCFETs), high electron mobility transistors (HEMTs), and heterostructure FETs (HFETs) with the same gate length and were mainly attributed to higher transconductance due to higher mobility, while the DC values were comparable with the other works. The above results suggested that Ga/sub 0.51/In/sub 0.49/P/In/sub 0.15/Ga/sub 0.85/As/GaAs doped channel FETs were were very suitable for microwave high power device application.

3–10-GHz Ultra-Wideband Low-Noise Amplifier Utilizing Miller Effect and Inductive Shunt–Shunt Feedback Technique

This paper reports the design and analysis of 21-29-GHz CMOS low-noise amplifier (LNA), balun and mixer in a standard 0.18-μm CMOS process for ultra-wideband automotive radar systems. To verify the proposed LNA, balun, and mixer architectures, a simplified receiver front-end comprising an LNA, a double-balanced Gilbert-cell-based mixer, and two Marchand baluns was implemented. The wideband Marchand baluns can convert the single RF and local oscillator (LO) signals to nearly perfect differential signals over the 21-29-GHz band. The performance of the mixer is improved with the current-bleeding technique and a parallel resonant inductor at the differential outputs of the RF transconductance stage. Over the 21-29-GHz band, the receiver front-end exhibits excellent noise figure of 4.6±0.5 dB, conversion gain of 23.7±1.4 dB, RF port reflection coefficient lower than -8.8 dB, LO-IF isolation lower than -47 dB, LO-RF isolation lower than -55 dB, and RF-IF isolation lower than -35.5 dB. The circuit occupies a chip area of 1.25×1.06 mm2, including the test pads. The dc power dissipation is only 39.2 mW.