Jin-Fa Chang

Analysis and Design of CMOS Distributed Amplifier Using Inductively Peaking Cascaded Gain Cell for UWB Systems

A low-power, high-gain (HG), and low-noise (LN) CMOS distributed amplifier (DA) using cascaded gain cell, formed by an inductively parallel-peaking cascode-stage with a low-Q RLC load and an inductively series-peaking common-source stage, is proposed. Flat and high S21 and flat and low noise figure (NF) are achieved simultaneously by adopting a slightly under-damped Q factor for the second-order transconductance frequency response. A single-stage and a two-stage DA for ultra-wideband (UWB) systems are demonstrated. In the LN mode, the two-stage DA consumes 22 mW and achieves flat and high S21 of 14.07 ± 1.69 dB with an average NF of only 2.8 dB over the 3-10-GHz band of interest, one of the best reported NF performances for a CMOS UWB DA or LN amplifier in the literature. In addition, in the low-gain mode, the two-stage DA consumes 6.86 mW and achieves S21 of 11.03 ± 0.98 dB and an average NF of 4.25 dB. In the HG mode, the two-stage DA consumes 37.8 mW and achieves S21 of 20.47 ± 0.72 dB and an average NF of 3.3 dB. The analytical, simulated, and measured results are mutually consistent.

A High-Performance Distributed Amplifier Using Multiple Noise Suppression Techniques

We demonstrate a 1.2-8.6 GHz two-stage distributed amplifier (DA) with cascade gain cell, which constitutes two enhanced CMOS inverters, using standard 0.18 μm CMOS technology. Multiple noise suppression techniques, including three noise-suppression/gain-peaking inductors and an RL terminal network, were used to achieve flat and low noise figure (NF) and flat and high power gain (|S21|) at the same time. At low-gain (LG) mode, the DA achieved |S21| of 11.41 ± 1.39 dB and an average NF of 3.74 dB for frequencies 1.2 ~ 8.6 GHz with a power dissipation (PDC) of 9.85 mW. At high-gain (HG) mode, the DA consumed 46.85 mW and achieved flat and high |S21| of 17.1 ± 1.5 dB with an average NF of 3.52 dB for frequencies 1.5 ~ 8.2 GHz.

Ultralow-Loss and Broadband Micromachined Transmission Line Inductors for 30–60 GHz CMOS RFIC Applications

In this paper, for the first time, we demonstrate that ultralow-loss and broadband transmission line (TL) inductors can be obtained by using the CMOS-process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the TL inductors. The results show that a 112.8% (from 14.37 to 30.58) and a 201.1% (from 6.33 to 19.06) increase in Q-factor, a 9.7% (from 0.91 to 0.998) and a 28.3% (from 0.778 to 0.998) increase in maximum available power gain GAmax, and a 0.404-dB (from 0.412 to 7.6times10-3 dB) and a 1.082-dB (from 1.09 to 8.4times10-3 dB) reduction in minimum noise figure NFmin were achieved at 30 and 60 GHz, respectively, for a 162.2 pH TL inductor after the backside ICP dry etching. The state-of-the-art performances of the on-chip TL inductors-on-air suggest that they are very suitable for application to realize ultralow-noise 30-60-GHz CMOS radio-frequency integrated circuit. In addition, the CMOS-process compatible backside ICP etching technique is very promising for system-on-a-chip applications.

A High-Performance Micromachined RF Monolithic Transformer With Optimized Pattern Ground Shields (OPGS) for UWB RFIC Applications

In this brief, we demonstrate that high-quality-factor and low-power-loss transformers can be obtained if the optimized pattern ground shields (OPGS) of polysilicon is adopted and the CMOS process-compatible backside inductively coupled-plasma (ICP) deep-trench technology is used to selectively remove the silicon underneath the transformers completely. OPGS means that the redundant PGS of a traditional complete PGS, which is right below the spiral metal lines of the transformer, is removed for the purpose of reducing the large parasitic capacitance. The results show that, if the OPGS was adopted and the backside ICP etching was done, a 69.3% and a 253.6% increase in quality factor, a 10.5% and a 14% increase in magnetic-coupling factor (kIm), a 17.2% and a 51.1% increase in maximum available power gain (GAmax), and a 0.682- and a 1.79-dB reduction in minimum noise factor (NFmin) were achieved at 5 and 8 GHz, respectively, for a bifilar transformer with an overall dimension of 230times215 mum2

A 60 GHz CMOS receiver front-end with integrated 180 ° out-of-phase wilkinson power divider

A 60-GHz receiver front-end with an integrated 180° out-of-phase Wilkinson power divider using standard 0.13 µm CMOS technology is reported. The receiver front-end comprises a wideband low-noise amplifier (LNA) with 12.4-dB gain, a current-reused bleeding mixer, a baseband amplifier, and a 180° out-of-phase Wilkinson power divider. The receiver front-end consumed 50.2 mW and achieved input return loss at RF port better than −10 dB for frequencies from 52.3 GHz to 62.3 GHz. At IF of 20 MHz, the receiver front-end achieved maximum conversion gain of 18.7 dB at RF of 56 GHz. The corresponding 3-dB bandwidth (ω3dB) of RF is 9.8 GHz (50.8 GHz to 60.6 GHz). The measured minimum noise figure (NF) was 9 dB at 58 GHz, an excellent result for a 60-GHz-band CMOS receiver front-end. In addition, the measured input 1-dB compression point (P1dB) and input third-order inter-modulation point (IIP3) are −20.8 dBm and −12 dBm, respectively, at 60 GHz. These results demonstrate the adopted receiver front-end architecture is very promising for high-performance 60-GHz-band RFIC applications.

A 4.9-dB NF 53.5–62-GHz micro-machined CMOS wideband LNA with small group-delay-variation

A 53.5–62-GHz wideband CMOS low-noise amplifier (LNA) with excellent phase linearity property is reported. Current-sharing technique is adopted to reduce power dissipation. The LNA (STD LNA) consumed 29.1 mW and achieved input return loss (S11) of −10.3∼ −19.5 dB, output return loss (S 22 ) of −13.8∼ −27.8 dB, forward gain (S 21 ) of 8.1∼ 11.1 dB, and reverse isolation (S 12 ) of −49.9∼ −60.2 dB over the 53.5–62-GHz-band. The minimum NF (NF min ) is 5.4 dB at 62 GHz. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to remove the silicon underneath the LNA. After the ICP etching, the LNA (ICP LNA) achieved maximum S 21 (S 21-max ) of 13.2 dB, 2.1 dB higher than that (11.1 dB) of the STD LNA. In addition, the ICP LNA achieved NF min of 4.9 dB, 0.5 dB lower than that (5.4 dB) of the STD LNA. These results demonstrate the proposed LNA architecture in conjunction with the backside ICP technology is very promising for 60-GHz-band RFIC applications.

High-Coupling and Ultra-Low-Loss Interlaced Stacked Transformers for 60-100 GHz CMOS RFIC Applications

In this paper, we demonstrate that high-coupling and ultra-low-loss transformers for 60-100 GHz CMOS RFIC applications can be achieved by using single-turn two-layer interlaced stacked (STIS) structure implemented in a standard CMOS technology. State-of-the-art G Amax of 0.711, 0.922, and ~1 (i.e. NFmin of 1.48, 0.35, and ~0 dB) were achieved at 60, 80, and 100 GHz, respectively, for a STIS transformer with an inner dimension of 50times50 mu2 and a metal width of 5 mum, mainly due to the high magnetic-coupling factor (klm) and the high resistive-coupling factor (kRe). In addition, a 94.1% (from 5.61 to 10.89) and a 196.8% (from 8.36 to 24.81) increase in Q-factor, a 14.2% (from 0.711 to 0.812) and a 8.5% (from 0.922 to ~1) increase in G Amax, and a 0.58 dB (from 1.48 dB to 0.90 dB) and a 0.35 dB (from 0.35 dB to ~0 dB) decrease in NFmin were achieved at 60 and 80 GHz, respectively, for the transformer after the post-process of proton implantation. The present analysis is helpful for RF engineers to design ultra-low-voltage high-performance 60-100 GHz transformer-feedback CMOS (or BiCMOS) LNAs and VCOs, and other RF-ICs which include transformers

A low-power 3.2∼9.7GHz ultra-wideband low noise amplifier with excellent stop-band rejection using 0.18µm CMOS technology

A low-power 3.2~9.7 GHz low-noise amplifier (LNA) with excellent stop-band rejection by 0.18 μm CMOS technology is demonstrated. High stop-band rejection is achieved by using a passive band-pass filter with three finite transmission zeros (in the input terminal of the common-gate LNA), one of which (ωz1 = 0.9 GHz) is in the low-frequency stop-band and the other two (ωz3 and ωz5) are in the high-frequency stop-band. In addition, an active notch filter is used in the output terminal of the LNA to introduce another low-frequency stop-band transmission zero (ωz2) at 2.4 GHz. The LNA consumes 4.68 mW and achieves S11 of -10~ -39.5 dB, S21 of 9.3±1.5 dB, and an average NF of 6 dB over the 3.2~9.7 GHz band. Moreover, the stop-band interferers can be effectively attenuated. The measured stop-band rejection is better than 21.6 dB for frequencies DC~2.5 GHz and 11.2~20 GHz. The corresponding stop-band rejection at 0.9 GHz, 1.8 GHz, 2.4 GHz, 17.6 GHz, and 19.5 GHz are 53.3 dB, 26.4 dB, 26.5 dB, 60 dB, and 59.5 dB, respectively.

A 2.76 mW, 3–10 GHz ultra-wideband LNA using 0.18 µm CMOS technology

A low-power (2.76 mW) common-gate (CG) low-noise amplifier (LNA) for ultra-wideband (UWB) systems using standard 0.18 µm CMOS technology is demonstrated. Instead of the traditional single parallel inductor (L<inf>S1</inf> only), we propose a new matching network consisting of a series L<inf>S1</inf>-R<inf>S1</inf> in series with a parallel L<inf>S2</inf>-RS<inf>2</inf> to enhance the input matching bandwidth. Flat and high S<inf>21</inf> was achieved by using the connecting inductor L<inf>C</inf> and the peaking inductor L<inf>D2</inf> to compensate the gain loss at medium-frequency and high-frequency, respectively. In addition, for suitable values of L<inf>C</inf> and L<inf>D2</inf>, flat and low NF (i.e. a nearly critically-damped Q-factor for the second-order NF frequency response) can also be achieved. Over the 3–10 GHz band of interest, the LNA achieved S<inf>21</inf> of 10.1±1.7 dB, minimum NF of 3.9 dB (at 4 GHz) and an average NF of 4.6 dB. The power dissipation was 2.76 mW, and the corresponding figure-of-merit (FOM) was 4.3. Both are of the best results ever reported for a CMOS UWB LNA.

A 18.85 mW 20–29 GHz wideband CMOS LNA with 3.85±0.25 dB NF and 18.1±1.9 dB gain

A 20–29 GHz wideband CMOS low-noise amplifier (LNA) with flat and low noise figure (NF), flat and high gain (S21), and excellent phase linearity property (group-delay-variation is only ±22.6 ps across the whole band) is demonstrated. To achieve flat and low NF, the size, layout and bias of the input transistor were first optimized for minimum NF, and then the inductance of the input inductors was tuned to obtain a slightly under-damped (flat) NF frequency response. In addition, to achieve flat and high S21 and small group-delay-variation, the inductive-peaking technique was adopted in the current-reused stage for bandwidth enhancement. The LNA consumed 18.85 mW power and achieved flat and low NF of 3.85±0.25 dB, and flat and high S21 of 18.1±1.9 dB over the 20–29 GHz band of interest. These are the best NF and S21 performances ever reported for a 21.65–26.65 GHz or a 22–29 GHz wideband CMOS LNA.