Valur Gudmundsson

Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation

Schottky-barrier source/drain (SB-S/D) presents a promising solution to reducing parasitic resistance for device architectures such as fully depleted UTB, trigate, or FinFET. In this letter, a low-temperature process (< 700degC) with PtSi-based S/D is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (tSi = 30 nm). Dopant segregation with As was used to achieve the n-type behavior at implantation doses of 1 ldr 1015 and 5 ldr 1015 cm-2. Similar results were found for UTB devices with both doses, but trigate devices with the larger dose exhibited higher on currents and smaller process variation than their lower dose counterparts.

Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts

This paper provides an overview of metallic source/drain (MSD) Schottky-barrier (SB) MOSFET technology. This technology offers several benefits for scaling CMOS, i.e., extremely low S/D series resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of this technology needs to overcome new obstacles such as Schottky barrier height (SBH) engineering and careful control of SALICIDE process. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. Recently, we have invested a lot of efforts on Pt- and Ni-silicide MSD SB-MOSFETs and achieved some promising results. The present work, together with the work of other groups in this field, places silicide MSD SB-MOSFETs as a competitive candidate for future generations of CMOS technology.

Error Propagation in Contact Resistivity Extraction Using Cross-Bridge Kelvin Resistors

The cross-bridge Kelvin resistor is a commonly used method for measuring contact resistivity (ρ<i>c</i>). For low ρ<i>c</i>, the measurement has to be corrected for systematic error using measurements of contact resistance, semiconductor sheet resistance, and device dimensions. However, it is not straightforward to estimate the propagation of random measurement error in the measured quantities on the extracted ρ<i>c</i>. In this paper, a method is presented to quantify the effect of random measurement error on the accuracy of ρ<i>c</i> extraction. This is accomplished by generalized error propagation curves that show the error in ρ<i>c</i> caused by random measurement errors. Analysis shows that when the intrinsic resistance of the contact is smaller than the semiconductor sheet resistance, it becomes important to consider random error propagation. Comparison of literature data, where ρ<i>c</i> <; 5 ·10^-8Ω · cm² has been reported, shows that care should be taken since, even assuming precise electrical data, a 1% error in the measurement of device dimensions can lead to up to ~ 50% error in the estimation of ρ<i>c</i>.

Direct measurement of sidewall roughness on Si, poly-Si and poly-SiGe by AFM

In this paper the effect of the commonly used HBr/Cl-2 chemistry for dry etching on the line-edge roughness (LER) of photoresist patterned single crystalline Si (sc-Si), polycrystalline Si (poly-Si ...

Effect of Be segregation on NiSi/Si Schottky barrier heights

The effect of Be segregation on the Schottky barrier heights (SBH) of NiSi/Si is studied. Many elements have been shown to modulate the SBH of NiSi. However, group II elements have, to our knowledge, not been investigated before. Be is a double acceptor in Si, making it interesting for SBH modulation towards the valence band. The results show that Be implantation did not change the silicidation process. The SBH modulation was found to be strongly dependent on the silicidation temperature, with a minimum barrier to the valence band Φbp=0.28±0.02 eV, for diodes formed at 600 °C. SIMS analysis show the Be dose left at the interface is very low. With such a low dose, modulation cannot be caused by an interface dipole. However, the results can be explained assuming a thin (∼4–5 nm) layer of activated Be close to the interface.

Integration of metallic source/drain (MSD) contacts in nanoscaled CMOS technology

An overview of metallic source/drain (MSD) contacts in nanoscaled MOSFET technology is provided in this paper. MSD contacts offer several benefits for nanoscaled CMOS, i.e., extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. In order to achieve high performance MSD MOSFETs, many design parameters such as Schottky barrier height (SBH), S/D to gate underlap, top Si layer thickness, oxide thickness and so on should be optimized. Recently, a lot of efforts have been invested in MSD MOSFETs based on Pt- and Ni-silicide implementation and several promising results have been reported in literature. The experimental work as well as the results of Monte Carlo simulations by this research team and by other research teams is discussed in this paper. It will be shown that the present results place MSD MOSFETs as a competitive candidate for future generations of CMOS technology.

Characterization of dopant segregated Schottky barrier source/drain contacts

In this paper, the gate-voltage dependent source/drain (S/D) resistance (RSD) in dopant segregated (DS) Schottky barrier (SB) junctions is examined by experiment and simulation. The focus is placed on fully depleted UTB-SOI MOSFETs featuring PtSi S/D with As-DS realized at low temperatures. When modeling SB-S/D with DS, it is challenging to determine if the performance enhancement observed is induced by a highly doped shallow layer in Si or by an interfacial dipole causing SB height lowering. The simulation reveals that the gate-voltage dependence of RSD is stronger for the dipole effect. For the SB-MOSFETs with DS-S/D examined in this work, the simulation gives an excellent fit to the measured data when SBH lowering is combined with high concentration shallow doping.

Towards Schottky-barrier source/drain MOSFETs

This paper provides an overview of metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology. The technology offers several benefits for scaling CMOS, i.e., extremely low source/drain resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of the technology needs to overcome new obstacles such as SB height engineering and precise control of silicide growth. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. In the past two years several groups have demonstrated high-performance SB MOSFETs, which places the technology as a promising candidate for future generations of CMOS technology.