Eugenio Dentoni Litta

Thulium Silicate Interfacial Layer for Scalable High-k/Metal Gate Stacks

Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25±0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-2×1011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm-2 and at a total capacitance equivalent thickness of 1.6 nm.

Integration of TmSiO/HfO 2 Dielectric Stack in Sub-nm EOT High-

Integration of a high-

k

k

/Metal Gate CMOS Technology

interfacial layer (IL) is a promising technological solution to improve the scalability of high-

Enhanced Channel Mobility at Sub-nm EOT by Integration of a TmSiO Interfacial Layer in HfO 2 /TiN High-k/Metal Gate MOSFETs

k

Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs

/metal gate CMOS technology. We have previously demonstrated a CMOS-compatible integration scheme for thulium silicate (TmSiO) IL and shown excellent characteristics in terms of equivalent oxide thickness (EOT), interface state density, channel mobility, and threshold voltage control. Here, we report on optimized annealing conditions leading to gate leakage current density comparable with state-of-the-art SiO x /HfO2 nFETs (0.7 A/cm

Recent advances in high-k dielectrics and inter layer engineering

^{2}

Low-Frequency Noise Characterization of Ultra-Low Equivalent-Oxide-Thickness Thulium Silicate Interfacial Layer nMOSFETs

at 1 V gate bias) at sub-nm EOT (as low as 0.6 nm), with near-symmetric threshold voltages (0.5 V for nFETs and −0.4 V for pFETs). We demonstrate an excellent performance benefit of the TmSiO/HfO2 stack, i.e., improved channel mobility over SiO x /HfO2 dielectric stacks, demonstrating high-field electron and hole mobility of 230 and 70 cm

Improved low-frequency noise for 0.3nm EOT thulium silicate interfacial layer

^{2}

High-Deposition-Rate Atomic Layer Deposition of Thulium Oxide from TmCp3 and H2O

/Vs, respectively, after forming gas anneal at EOT = 0.8 nm. Finally, the reliability of the TmSiO/HfO2/TiN gate stack is investigated, demonstrating 10-year expected lifetimes for both oxide integrity and threshold voltage stability at an operating voltage of 0.9 V.