Pete Sivonen

A 1.2-V Highly Linear Balanced Noise-Cancelling LNA in 0.13-

In this paper, a current-to-voltage combiner is proposed to realize a highly linear, balanced noise-cancelling low-noise amplifier (LNA) capable of low-voltage operation. The current-to-voltage combiner, implemented in the load of the amplifier, converts the output currents of the parallel common-gate (CG) and common-source (CS) stages of the LNA to voltages, equalizes the amplitudes of the voltages, and combines the voltages to a single output voltage. Since only a CS stage and passive components are employed to cancel the noise and distortion due to the CG input impedance matching circuit, high linearity is achieved in spite of the low supply voltage of 1.2 V. The LNA achieves a noise figure (NF) of 3.0 dB at 2.1 GHz with an input-referred third-order intercept point (IIP3) of +10.5 dBm while consuming 10.5 mA from a 1.2-V supply. The amplifier is fabricated in 0.13-mum CMOS process.

\mu{\hbox{m}}

The effects of packaging in inductively degenerated common-source low-noise amplifiers (LNAs) with electrostatic discharge (ESD) protection are studied and the performance of the packaged LNA is optimized. Equations describing the input impedance, transconductance, voltage gain, and noise figure (NF) of the packaged amplifier are derived and the effects of the LNA input matching network, package, and ESD parasitics on these amplifier quantities are highlighted. From the equations, several design guidelines for the packaged LNA are obtained and a systematic approach for the ESD-protected LNA optimization is deduced. It is also shown that, in the presence of an equivalent parallel package parasitic capacitance C/sub p/, the NF in a well-optimized LNA is easily dominated by the losses of the input-matching network instead of the active device noise. Based on the theoretical results, a packaged inductively degenerated common-source LNA with ESD protection is designed in a 0.13-/spl mu/m CMOS process. The amplifier provides a forward gain (S/sub 21/) of almost 18 dB at 2 GHz with an NF of 1.6 dB while consuming 8.4 mW from a 1.2-V supply.

CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.

Analysis and optimization of packaged inductively degenerated common-source low-noise amplifiers with ESD protection

The effects of packaging on the performance of inductively degenerated common-emitter low-noise amplifiers (LNAs) are examined and the equations describing the input impedance, transconductance, voltage gain, and noise figure of the packaged amplifier are derived. From the equations, several guidelines for the LNA design are obtained and a systematic approach for the LNA design can be derived. Furthermore, by applying the formulas, the performance of the amplifier can be readily estimated and optimized in the very early stage of the circuit design, immediately as the process data is available. The measurement results of the implemented 0.35-/spl mu/m SiGe RF front-end with an inductively degenerated common-emitter LNA at 1.575 GHz agree well with calculations and simulations.

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a biasing technique for cancelling second-order intermodulation (IM2) distortion and enhancing second-order intercept point (IIP2) in common-source and common-emitter RF transconductors is presented. The proposed circuit can be utilized as an RF input transconductor in double-balanced downconversion mixers. By applying the presented technique, the achievable IIP2 of the mixer is limited by the linearity of the switching devices, component mismatches, and offsets. The proposed circuit has properties similar to the conventional differential pair transconductor in that it ideally displays no IM2 distortion. However, the presented circuit is more suitable for operation at low supply voltages because it has only one device stacked between the transconductor input and output. In the conventional differential pair, two devices consume the voltage headroom. The noise performance of the proposed transconductor is similar to the noise performance of the traditional common-source (emitter) and differential pair transconductors at given bias and device dimensions. On the other hand, the third-order intercept point (IIP3) of the presented transconductor is slightly higher than the IIP3 of the differential pair transconductor at given bias. Finally, the proposed circuit can also be employed as a current mirror, the ratio of which is very insensitive to the voltage swings at the gate or base of the current mirrored transistor.

Analysis of packaging effects and optimization in inductively degenerated common-emitter low-noise amplifiers

A gain stabilization technique for tuned integrated low-noise amplifiers (LNAs) is presented. The proposed method regulates the LC-tuned load impedance of the amplifier at the operation frequency against variations of passive devices in integrated circuit (IC) process. The impedance stabilization technique is based on the excellent relative accuracy of integrated resistors. Although the absolute deviation of the integrated resistors can be as large as /spl plusmn/20%, the relative deviation can be made smaller than /spl plusmn/1% provided that resistors are placed close to each other. By applying the proposed method, the voltage-gain variation of the inductively degenerated common-source LNA, which is the most popular LNA architecture, can be reduced several decibels. As a consequence, the entire radio receiver can more easily meet its specifications in the presence of IC process variations and the product yield is improved. Finally, besides the LNAs, the presented stabilization technique can also be utilized in other tuned amplifiers, filters or oscillators employing damped LC-tuned loads.