Sami Kallioinen

A Multimode Transmitter in 0.13

This paper presents a system-independent transmitter architecture based on a direct-digital RF-modulator which combines the D/A conversion, up-conversion, unwanted sideband rejection, power control, and part of the digital image-rejection filtering into a single mixed-signal circuit block. The multimode capability of the architecture is demonstrated with WCDMA, EDGE, and WLAN system requirements. The modulator achieves 90 dB of power control range and with an external power amplifier module, WCDMA EVM of less than 2% from signal powers of -20 dBm to +25 dBm. The noise floor level defined by the quantization noise at 190 MHz offset from the carrier is -150 dBc/Hz measured at the output of the PA with +25 dBm signal power. The analog power consumption with the maximum signal power level is 92 mW and scales down to 46 mW when reducing the signal level to -43 dBFS. The digital power consumption is 65 mW. The chip is implemented with a standard 0.13 mum 1.2 V digital CMOS with total silicon area of 4 mm2.

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Direct delta-sigma receiver architecture is introduced for wireless communication systems, such as LTE or WiMax. Architecture is based on direct downconversion, delta-sigma feedback that is up-converted to RF, and N-path filtering technique. Hence, the core receiver functions including channel selection filtering are embedded to a RF ADC with excellent linearity performance. This is achieved by transforming narrow-band filtering partially to RF injecting feedback into the input of the second amplifier stage, hence relieving requirements of the most critical subsequent stages. A 900-MHz direct delta-sigma receiver prototype occupies an active area of 1.2 mm2 in 65-nm CMOS. The receiver for low-band cellular operations achieves NF of 2.3 and 6.2 dB in conventional and delta-sigma modes, respectively, and out-of-band IIP3 up to +4 dBm when the delta-sigma loop is active. The chip consumes 80 mW from a 1.2-V supply.

CMOS Using Direct-Digital RF Modulator

Spectrum sensing is needed in cognitive radios to provide information about the surrounding radio spectrum. This enables cognitive radio system to communicate among existing radio systems without interfering them. This paper describes an FPGA implementation of a cyclostationary feature detector, which has an improved detection performance achieved by decimation of the cyclic spectrum. Decimation also provides a simple way to control detection time and, thus, allows trading the detection time to better probability of detection and vice versa. Measured detection performance is presented and detection of a 802.11g WLAN signal from air is demonstrated.

A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS

This paper presents what kind of challenges are posed when a global positioning system (GPS) receiver is being added to a multiradio terminal. The GPS receiver chain is integrated as a part of a multiband and multimode receiver, designed for global system for mobile communications (GSM) and wideband code division multiple access (WCDMA). The hostile radio environment challenges in a terminal level are discussed. Especially, the modifications of the additional GPS mode to an existing receiver ASIC with minor and most necessary changes to the implementation is discussed and presented. The IC is implemented in a 0.13-mum CMOS technology without any analog options. At 1.2-V supply voltage and total power dissipation of 49 mW for the analog signal path, the proposed GPS receiver features a noise figure of 2.2 dB and an out-of-band IIP3 of +24 dBm for the worst-case test scenario, which makes it suitable to cellular handset usage in a demanding interference environment.

Implementation of Cyclostationary Feature Detector for Cognitive Radios

This paper presents a wideband blocker filtering technique for an RF front-end. A wideband LNA and a transferred impedance filter are implemented as part of a receiver to demonstrate the feasibility of the system. The transferred impedance filter includes an adjustable polyphase filter to compensate for the phase shift in the system in order to maintain correct operating frequency. The transferred impedance filter with passive mixers and the wideband LNA are analyzed by means of frequency transformation to demonstrate the different design trade-offs. The front-end achieves a gain of 43 and 41 dB and a noise figure of 3.2 and 5.7 dB with an IIP3 of -13 and -5 dBm with the transferred-impedance filter turned off and on, respectively. An added selectivity of 6 dB is achieved by using the solutions described in this paper.

A Low Noise Figure 1.2-V CMOS GPS Receiver Integrated as a Part of a Multimode Receiver

Spectrum sensing is one of the most challenging task in implementing future cognitive radios. The sensing unit should provide reliable information about the surrounding radio spectrum with small delay and low power consumption. This paper presents an implementation of a spectrum sensing unit capable of performing both cyclostationary feature detection and spectrum estimation for energy detection. A prototype is designed on a FPGA for measurement and demonstration, and synthesis for 65 nm CMOS process provides estimates for area and power consumption in an ASIC implementation.

Wideband 2 to 6 GHz RF Front-End With Blocker Filtering

A WCDMA transmitter based on direct-digital RF modulator has a power control range of >90dB and achieves an ACPR of -58dBc with a channel power of -2dBm. Using an external PA with a power gain of 27dB, the measured EVM is <2% with signal levels from -35 to +25dBm. The chip is fabricated in a 0.13μm 1.2V CMOS process and occupies 4mm2.

Spectrum estimator and cyclostattionary detector for cognitive radio

This paper presents a wideband blocker filtering technique for a RF front-end. The wideband LNA and the transferred impedance filter are implemented as part of a receiver to demonstrate the feasibility of the system. The front-end achieves a gain of 43 and 41 dB, noise figure of 3.2 and 5.7 dB with IIP3 of −13 and −5 dBm with the transferred-impedance filter turned off and on, respectively. Added selectivity of 6 dB is achieved by using the structure described in this paper.

A WCDMA Transmitter in 0.13μm CMOS Using Direct-Digital RF Modulator

A 900 MHz direct-conversion receiver with a ΔΣ feedback loop to RF occupies an active area of 1.2 mm² in 65 nm CMOS. The concept prototype for low-band cellular operations achieves NF of 2.3 and 6.2 dB in conventional and ΔΣ modes, respectively, and out-of-band IIP3 up to ±4 dBm when the ΔΣ loop is active. The chip consumes 80 mW from a 1.2 V supply.