Peter Celinski

State-of-the-art in CMOS threshold-logic VLSI gate implementations and applications

In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in CMOS. This paper presents a summary of the recent developments in TL circuit design. High-performance TL gate circuit implementations are compared, and a number of their applications in computer arithmetic operations are reviewed. It is shown that the application of TL in computer arithmetic circuit design can yield designs with significantly reduced transistor count and area while at the same time reducing circuit delay and power dissipation when compared to conventional CMOS logic.

Delay analysis of neuron-MOS and capacitive threshold-logic

A model for the delay of neuron-PMOS (neu-MOS) and Capacitive Threshold-Logic (CTL) based logic circuits is presented for the first time. It is based on the analysis of the basic neuron-MOS and CTL gate structures. A closed form analytic expression for the delay of the threshold gate is derived. A relation for the delay in terms of an ordinary CMOS inverter delay expressed as a function of the number of inputs to the threshold gate is presented. This relation is shown to be useful in comparing the delay of logic circuit designs based on neu-MOS or CTL and ordinary CMOS.

Low depth carry lookahead addition using charge recycling threshold logic

The main result of this paper is the development of a low depth carry lookahead addition technique based on threshold logic. Two such adders are designed using the recently proposed charge recycling threshold logic gate. The adders are shown to have a very low logic depth, and significantly reduced area and power dissipation compared to other dynamic CMOS implementations.

Low depth, low power carry lookahead adders using threshold logic

This paper describes a low power threshold logic-gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. This is followed by the main result, which is the development of a novel, low depth, carry lookahead addition scheme based on threshold logic. One such adder is also designed and simulated using the proposed gate.

Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/threshold-logic approach

This paper presents the design exploration of CMOS 64-bit adders designed using threshold logic gates based on systematic transistor level delay estimation using logical effort (LE). The adders are hybrid designs consisting of domino and the recently proposed charge recycling threshold logic (CRTL). The delay evaluation is based LE modelling of the delay of the domino and CRTL gates. From the initial estimations, we select the 8-bit sparse carry lookahead/carry-select scheme. Simulations indicate a delay of less than 5 FO4 or 17% faster than the nearest domino design.

Area efficient, high speed parallel counter circuits using charge recycling threshold logic

The main result is the development of a low depth, highly compact implementation of parallel counters (i.e., population counters), based on threshold logic. Two such counters are designed using the recently proposed Charge Recycling Threshold Logic (CRTL) gate. The novel feature of the designs is the sharing among all threshold gates of a single capacitive network for computing the weighted sum of all input bits. The significance of the result is the reduction by almost 35% in the required number of capacitors for the (7,3) counter and by over 60% for the (15,4) counter. This reduces the total area by approximately 37% for the (7,3) counter and by 60% for the (15,4) counter, with no increase in delay. The proposed (7,3) counter design is also shown to be 45% faster compared to a conventional Boolean full-adder based circuit.

Hybrid parallel counters - domino and threshold logic

Parallel counters are the building blocks of partial product reduction tree (PPRT) circuits, which are required for high-performance multiplication. In this paper we will implement novel counters using a hybrid of domino and threshold logic. A test 64 /spl times/ 64 PPRT using these counters was found to reduce latency by 39% and device count by 38% compared to the domino logic equivalent.

A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder

A high speed 64-bit dynamic adder, the Adelaide-Delft Threshold Logic Adder (A-DELTA), is presented. The adder is based on a hybrid carry-lookahead/carry-select scheme using threshold logic and conventional CMOS logic. A-DELTA was designed and simulated in a 0.35 μm process. The worst case critical path latency is 670 ps, which is shown to be on average 30% faster than previously proposed high speed Boolean dynamic logic adders while at the same time reducing the transistor count on average by over 30% compared to the same adders.

Optical threshold logic analog-to-digital converters using self electro-optic effect devices

A novel 2-bit optical-input optical-output analog-to-digital converter (ADC) is demonstrated in self electro-optic device (SEED) technology using a threshold logic technique. The threshold gate was constructed using a resistor-SEED (R-SEED) which is composed of a large value resistor and a SEED area of 500 um x 500 um. Each gate operates as a majority function that has a threshold level controlled by a fixed optical input. The ADC was constructed using two R-SEED gates operating at wavelength of 846 nm. The test bench set-up operates at 100 Hz. However, as the proposed architecture is scalable, it can operate at much higher speeds and generate larger number of bits. This architecture is only limited by the switching speed of the SEED and propagation delay through each threshold gate.

Threshold logic parallel counters for 32-bit multipliers

In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon. Threshold Logic enables, in some instances, the design of digital integrated circuits with a significantly reduced transistor count and area. This paper addresses the important problem of designing technologically feasible parallel (m,n) counters for using TL for binary multiplication. A number of counter design techniques are reviewed and some novel parallel counter designs are presented that allow the design of area efficient 32-bit multiplier partial product reduction circuits.