Peter Nunan
Varian Semiconductor
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Publication
Featured researches published by Peter Nunan.
ION IMPLANTATION TECHNOLOGY: 16th International Conference on Ion Implantation Technology - IIT 2006 | 2006
Steven R. Walther; Scott Falk; Sandeep Mehta; Yuri Erokhin; Peter Nunan
The cost of new process development has risen significantly with larger wafer sizes and the increased number of fabrication steps needed to create advanced devices. The high value of each 300 mm development wafer has spurred efforts to find a way to explore more than a single process setting with each wafer. Traditional methods of defining multiple spatially distinct implant regions on a single wafer achieve poor utilization of device die. The need for efficient utilization of the die and wide process latitude for defining multiple implant regions per wafer has led to the development of an implant proximity mask (vMask™), which permits sharply defined borders between implant regions that may have different species, energy, angle, or dose. The capability of this system to achieve multiple spatially resolved implant conditions per wafer with high die utilization and using the same process parameters as production implants will be described. Specifically, results for measurement of the uniform process area, ...
ION IMPLANTATION TECHNOLOGY: 16th International Conference on Ion Implantation Technology - IIT 2006 | 2006
Yuri Erokhin; Terry Romig; Elshot Kim; JieJie Xu; Baonian Guo; Jinnig Liu; Kyu-Ha Shim; Peter Nunan
As CMOS devices shrink they become increasingly sensitive to variations of ion beam angular properties and beam current density. In sub‐65 nm devices beam divergence and beam steering variations at levels commonly seen in high current implanters for Source/Drain Extension (SDE) implants could significantly shift device characteristics compromising yield and robustness of manufacturing process. In this paper we review the implant precision requirements for Source/Drain Extension (SDE) formation for sub‐65nm node devices. TCAD simulation was used to analyze the effects of beam divergence and steering errors for an on‐axis (0°) SDE implant on sub‐65 nm NMOS HP devices. Effects of energy contamination introduced along with decelerated low energy ions in p‐type SDE implants in PMOS devices is also discussed. Response of device electrical characteristics to variation of beam angle properties is quantified and beam angle control requirements for state‐of‐the‐art ultra‐low energy implanters formulated.
Archive | 2008
Paul Sullivan; Peter Nunan; Steven R. Walther
Archive | 2008
Yuri Erokhin; Paul Sullivan; Steven R. Walther; Peter Nunan
Archive | 2006
Peter Nunan; Anthony Renau; Alan Sheng; Paul J. Murphy; Kyu-Ha Shim; Charles Teodorczyk; Steven M. Anella; Samuel M. Barsky; Lawrence Ficarra; Richard J. Hertel
Archive | 2007
Yuri Erokhin; Steven R. Walther; Peter Nunan
Archive | 2006
Peter Nunan; Bret W. Adams
Archive | 2010
Peter Nunan; Gregory Redinbo; Julian G. Blake; Paul S. Buccos
Archive | 2008
Peter Nunan; Steven R. Walther; Yuri Erokhin
Archive | 2008
Peter Nunan; Steven R. Walther; Yuri Erokhin; Paul Sullivan