Yuri Erokhin

Schottky barrier height tuning of silicides on p-type Si (100) by aluminum implantation and pulsed excimer laser anneal

We investigate the tuning of Schottky barrier height (SBH) of nickel silicide formed by pulsed excimer laser anneal of nickel on silicon implanted with aluminum (Al). A wide range of laser fluence was investigated, and it has been found that laser fluence influences the distribution of Al within the silicide and at the silicide/silicon interface. This in turn affects the effective whole SBH (ΦBp) at the silicide/silicon junction. High Al concentration at the silicide/silicon interface and high temperature for nano-second duration to achieve Al activation while keeping the Al concentration within the silicide low is vital for achieving low ΦBp. We demonstrate the achievement of one of the lowest reported ΦBp of ∼0.11 eV. This introduces a new option for forming nickel silicide contacts with reduced contact resistance at low thermal budget for possible adoption in future metal-oxide-semiconductor transistor technologies.

Using Multiple Implant Regions To Reduce Development Wafer Usage

The cost of new process development has risen significantly with larger wafer sizes and the increased number of fabrication steps needed to create advanced devices. The high value of each 300 mm development wafer has spurred efforts to find a way to explore more than a single process setting with each wafer. Traditional methods of defining multiple spatially distinct implant regions on a single wafer achieve poor utilization of device die. The need for efficient utilization of the die and wide process latitude for defining multiple implant regions per wafer has led to the development of an implant proximity mask (vMask™), which permits sharply defined borders between implant regions that may have different species, energy, angle, or dose. The capability of this system to achieve multiple spatially resolved implant conditions per wafer with high die utilization and using the same process parameters as production implants will be described. Specifically, results for measurement of the uniform process area, ...

Device scaling and performance improvement: Advances in ion implantation and annealing technologies as enabling drivers

The complexity of ion implant applications in IC fabrication has grown significantly since becoming the preferred process for doping semiconductors. Aggressive device scaling over the last decade raised unique challenges. This resulted in the invention of novel implant applications to address device scaling driven issues and the development of new generations of ion implanters. These newly developed tools are capable of delivering a wide variety of ion beams of traditional doping and non-doping species, with manufacturing worthy beam currents over an energy range extending from 200 eV to several MeV. They are capable of controlling implanted wafer temperature down to cryogenic conditions to take full advantage of new defect engineering approaches. All these innovations resulted in significant growth of ion implantation steps in advanced IC manufacturing for both doping and Precision Materials Modification (PMM). In this paper we present an overview of recent advances in ion implantation technologies and applications addressing sub-20nm device and process integration challenges. We illustrate how these innovations enable improvement of device performance and expansion of process margins through novel capabilities of ion implantation tools coupled with innovative materials engineering approaches for junction formation and for process modules beyond of traditional doping applications.

Precision Implant Requirements for SDE Junction Formation in sub-65 nm CMOS Devices

Sub-65 nm devices are becoming increasingly sensitive to variations of ion beam angular properties. Beam divergence and beam steering effects in source/drain extension (SDE) implants could significantly shift device characteristics. In this paper we review the implant precision requirements for source/drain extension (SDE) formation for sub-65 nm node devices. TCAD simulation was used to analyze the effects of beam emittance and steering errors for an on-axis (0deg) SDE implant. In addition, the effect of energy contamination introduced along with decelerated low energy ions is also discussed. Response of device electrical characteristics to variation of beam angle properties is quantified and beam angle control requirements for state-of-the-art ultra-low energy implanters are formulated

Enhancing tensile stress and source/drain activation with Si:C with innovations in ion implant and millisecond laser spike annealing

Strain engineering has become a workhorse in increasing charge carrier mobility to boost performance for sub-45nm CMOS logic technologies. While pFET transistors with embedded Si1−xGex layers in the S/D region have been widely employed to induce compressive strain in the silicon channel, nFET transistors have mostly depended on either tensile liners or stress memorization techniques (SMT) to introduce tensile strain. Recently, there have been reports on the use of Si:C in the nFET S/D enhancing transistor performance. In this paper we discuss results from novel ion implantation schemes employed to maximize carbon incorporation and to achieve defect free, strained Si:C layers. In addition, high activation of the dopant is maintained even in the presence of relatively high carbon incorporation. Several anneal techniques including SPE anneal, spike RTP, and laser spike anneals have been used to optimize carbon incorporation, strain and activation. Results from these different anneal techniques will be compared and discussed.

Process Transferability from a Spot Beam to a Ribbon Beam Implanter: CMOS Device Matching

The exercise of dose and energy matching is the standard way to integrate a new implanter into a manufacturing fab. Sheet resistance and secondary‐ion mass spectroscopy (SIMS) measurements on bare silicon wafers have been the conventional metrologies to establish dose/energy equivalence between implanters. Invariably, matched performance on bare silicon wafers translated into matched device performance between implanters of the same kind. However, as devices scale down to 90 run and beyond, the implanter design can become a significant factor in terms of process matching. In this paper we discuss the dynamics of transferring 120–90nm logic processes from a traditional batch, spot beam implanter to a single wafer (SW), parallel ribbon beam implanter. The results show that the traditional approach to dose matching involving the basic parameters of specie, dose and energy, although necessary, is inadequate to provide matched device performance between the two implanter types. 3‐dimensional effects which cann...

High Current Implant Precision Requirements for Sub‐65 nm Logic Devices

As CMOS devices shrink they become increasingly sensitive to variations of ion beam angular properties and beam current density. In sub‐65 nm devices beam divergence and beam steering variations at levels commonly seen in high current implanters for Source/Drain Extension (SDE) implants could significantly shift device characteristics compromising yield and robustness of manufacturing process. In this paper we review the implant precision requirements for Source/Drain Extension (SDE) formation for sub‐65nm node devices. TCAD simulation was used to analyze the effects of beam divergence and steering errors for an on‐axis (0°) SDE implant on sub‐65 nm NMOS HP devices. Effects of energy contamination introduced along with decelerated low energy ions in p‐type SDE implants in PMOS devices is also discussed. Response of device electrical characteristics to variation of beam angle properties is quantified and beam angle control requirements for state‐of‐the‐art ultra‐low energy implanters formulated.

Predictive process simulation of cryogenic implants for leading edge transistor design

Two cryogenic implant TCAD-modules have been developed: (i) A continuum-based compact model targeted towards a TCAD production environment calibrated against an extensive data-set for all common dopants. Ion-specific calibration parameters related to damage generation and dynamic annealing were used and resulted in excellent fits to the calibration data-set. (ii) A Kinetic Monte Carlo (kMC) model including the full time dependence of ion-exposure that a particular spot on the wafer experiences, as well as the resulting temperature vs. time profile of this spot. It was calibrated by adjusting damage generation and dynamic annealing parameters. The kMC simulations clearly demonstrate the importance of the time-structure of the beam for the amorphization process: Assuming an average dose-rate does not capture all of the physics and may lead to incorrect conclusions. The model enables optimization of the amorphization process through tool parameters such as scan speed or beam height.

Schottky barrier height modulation with Aluminum segregation and pulsed laser anneal: A route for contact resistance reduction

We report the first demonstration of a contact technology employing a combination of low energy Aluminum (Al) ion implantation and pulsed laser anneal (PLA) to form nickel silicide (NiSi) with low hole effective Schottky barrier height (Φ<inf>B</inf>^p) on Si. First, the Al implant energy is reduced over prior work to ensure compatibility with thinner NiSi contacts. Second, the effect of PLA on silicide contact formation is investigated. Third, we show that increasing Al concentration at the silicide/Si interface while keeping the Al concentration within the silicide low is vital for reducing Φ<inf>B</inf>^p. Successful implementation of the contact technology leads to ~77 % reduction in Φ<inf>B</inf>^p, achieving a low Φ<inf>B</inf>^p of 0.104 eV. This opens up new options to lower Φ<inf>B</inf>^p with reduced thermal budget for future technology generations.

Impact of Dose Rate Effects and Damage Engineering on Device Performance

Traditional implant conditions during source/drain formation process, such as dopant, dose, energy and incident angle have been known as key parameters determining device electrical characteristics. As devices scale down, instant dose rate of BF2 ion implantation, however, should be considered as an important factor to control buried channel PMOS characteristics since fluorine and boron diffusion behavior can be varied depending on implant damage and results in change of effective channel length. Ribbon beam single wafer high current implanters enable ion beam density to be modulated. By changing beam size with same beam current during source/drain implantation, PMOS electrical characteristics of 70nm Flash memory have been investigated. With achieved results, device matching to spot beam batch ion implanter has been demonstrated.