Dusan D Milosevic

Wireless Body Area Networks

The main design challenge for sensor nodes used in a WBAN is a low power consumption. System level aspects play an important role in the overall power consumption of body area networks. In this chapter different sensor network aspects and reported WBAN applications are analyzed and summarized. Additionally, several MAC protocols are compared using the WBAN properties. Since low power consumption is of primary importance, the sensor node energy consumption of the different MAC-layers are compared. With the energy consumption models, the solution space is examined. At the end of the chapter the receiver requirements are obtained.

Intermodulation products in the EER technique applied to class-E amplifiers

Envelope elimination and restoration is a relatively old but attractive transmitter technique for high efficiency linear amplification of variable envelope RF signals. EER employs switching mode power amplifiers, which are extremely nonlinear but efficient, and the concept of supply voltage modulation to achieve linear performance. The bandwidth limitations in the envelope modulation path will have a strong impact on performance of the whole EER system. This paper derives analytic relationships between the transfer function in the envelope path of the EER system and IMD products in the output signal. The derived expressions are of generic character and can be used for an arbitrary transfer function in the envelope path. An estimation of the theoretical limit for IMD levels in the EER system based on the class-E amplifier is given.

Experimental Evaluation of an Adaptive Nonlinear Interference Suppressor for Multimode Transceivers

In multimode transceivers, the transmitter for one communication standard may induce a strong interference in the receiver for another standard. Using linear filtering techniques to suppress this interference requires a receiver with a very large dynamic range, leading to an excessive power consumption. A much more power efficient approach suppresses the interference using an adaptive nonlinear interference suppressor (NIS). In previous work an ideal model was used to derive an adaptation method and study the receiver performance afforded by the NIS. In this paper, we present experimental results of a receiver that uses an implementation of the NIS, fabricated in 140 nm complementary metal-oxide-semiconductor technology. Main imperfections that limit the NIS performance are identified, simple models are developed that explain the experimental results, and for the key imperfections, low-complexity digital compensation and calibration methods are proposed. These digital methods permit the use of lower-performance analogue circuits, thus further reducing the transceiver cost and power consumption. The experimental results show that the NIS can achieve a substantial interference suppression at attractive complexity and power dissipation.

A 1.8GHz amplifier with 39dB frequency-independent smart self-interference blocker suppression

This paper presents a 1.8GHz RF amplifier implemented in 140nm CMOS with frequency-independent blocker suppression. The functionality is obtained by adaptation of a nonlinear current transfer according to the blocker amplitude. In the presence of a 0-11dBm RF blocker a voltage gain of 7.6 to 9.4dB and IIP3 >;4dBm are measured, while the blocker is suppressed by more than 39dB. In case of no blocker the circuit is set to amplifier mode providing 17dB of voltage gain, 8.4dB noise figure and IIP3 of 6.6dBm while consuming 3mW. Application areas are coexistence in multi-radio devices and dealing with TX leakage in FDD systems.

Ultra-low power FSK receiver for body area networks with automatic frequency control

In this paper we present an ultra-low-power receiver geared towards body area networks (BAN). The presented wideband-FSK receiver consumes only 382.5μW while achieving a BER of 10-3 at -81dBm sensitivity for 12.5kbps. The bit rate is scalable up to 625kbps, enabling a trade-off between sensitivity and bit rate. Taking advantage of the short-range nature of BAN applications, a mixer-first architecture is proposed, leading to a good dynamic range, given the DC power consumption. To further decrease the power consumption a free-running digitally controlled oscillator (DCO), tunable from 782MHz to 932MHz, is implemented, that is controlled by a data-aided automatic frequency control (AFC) loop, making the receiver resilient against DCO frequency variations.

A 16–43 GHz low-noise amplifer with 2.5–4.0 dB noise figure

This paper presents an ultra-broadband low-noise amplifier (LNA) operating from 16 to 43 GHz in a 0.25 pm SiGe:C BiCMOS technology. Across this band, the LNA achieves simultaneous low-noise performance (2.5–4.0 dB) and power matching (S11 < −10 dB) using dual-LC tank matching. The measured minimal noise figure is 2.5 dB at 26 GHz with an average value of 3.25 (±0.75) dB from 16 to 44 GHz. The best gain is 10.5 dB at 26 GHz with a 3-dB gain bandwidth from 16 to 43 GHz (90% fractional bandwidth). The measured input 1-dB compression point and input IP3 are better than −8.5 dBm and 1.8 dBm over the 16–43 GHz band, respectively, for a total power consumption of 24 mW.

A 50 – 60 GHz rectifier with −7dBm sensitivity for 1 V DC output voltage and 8% efficiency in 65-nm CMOS

This paper presents a 50 - 60 GHz fully integrated 3-stage rectifier in 65nm CMOS technology. The sensitivity of the rectifier is the limiting factor for an on-chip wireless-powered receiver in CMOS technology. In this paper, the technique of body-drain connection is proposed and implemented. In this method, the parasitic diode is shorted and the threshold voltage of the MOSFET is modulated, improving the sensitivity. Compared to the inductor peaking method [1] and other mm-wave rectifiers [2][3] in CMOS technology, the circuit proposed in this paper achieves high sensitivity and efficiency while maintaining a compact size, because no inductors are used inside the rectifier. The work achieves the peak sensitivity at 52 GHz, providing a 1-V dc output voltage for an input power of -7 dBm. The overall sensitivity over the entire operational range of 50 - 60 GHz is below - 2 dBm.

Wake-up receiver based ultra-low-power WBAN

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A design of 2.4GHz rectifier in 65nm CMOS with 31% efficiency

This paper presents the analysis, the efficiency optimization and the design strategy of a Dickson type rectifier using 65nm CMOS technology. The rectifier is used as an on-chip wireless power receiver for wireless power transfer applications. The modeling of this rectifier takes the threshold voltage variation, bulk modulation, and the major parasitic capacitors into account. A mathematical model of the rectifier allows finding the relationship between its performance and the design parameters. Based on parameter discussion and performance analysis, a design procedure is presented to get higher conversion efficiency.

Increasing Isolation Between Colocated Antennas Using a Spatial Notch

This letter presents an antenna configuration to achieve a coupling reduction between colocated antennas. Application of an adaptive spatial notch enables this functionality. Analytical results are obtained, which show good resemblance to simulated and measured results, performed on a prototype manufactured to operate around 2.5 GHz. Coupling reduction of 50 dB has been measured. The antenna impedance is also influenced because of this configuration and shows an S11 better than - 15 dB at the frequency of interest. In addition, the radiation pattern of both antennas is influenced. This can be seen as an advantage or a disadvantage, depending on the application.