Ph. Jansen

Consistent small-signal and large-signal extraction techniques for heterojunction FET's

A new method is reported to extract large-signal current and charge sources from the small-signal S-parameters of pseudomorphic heterojunction field effect transistors (PHFETs). This method produces a new intrinsic small-signal equivalent circuit topology with less constraints concerning the extraction of the large-signal current and charge sources. The main advantage of this new topology is charge conservation. The S-parameter measurements of a 0.2-/spl mu/m PHFET agrees well with the small-signal S-parameter data, obtained after evaluation of the new large-signal model at different bias points. >

RFCMOS ESD protection and reliability

This paper addresses the ESD reliability issues in RFICs, focusing on the technology impact on the device and design. We also present the basic RF ESD protection methods used in industry. Presents the general topology of a 5 GHz LNA, which is protected using several ESD protection methodologies, and describes the 90 nm CMOS process technology used for the fabrication of the LNA. The measurement procedures used for the evaluation of stand-alone devices and LNAs are described. The ESD performance of standard ESD protection devices is reviewed and presents results and discussions on the ESD reliability of various ESD protection methods employed from the device point of view, followed by an outlook on the future RF ESD challenges, and conclusions.

Migration of Si in molecular-beam epitaxial growth of δ-doped GaAs and Al0.25Ga0.75As

We have analyzed the incorporation of Si δ doping during the molecular‐beam epitaxial (MBE) growth of GaAs and Al0.25Ga0.75As using secondary‐ion mass spectroscopy. At high substrate temperatures (≥580 °C) a significant and asymmetric broadening is observed in both GaAs and Al0.25Ga0.75As. This is due to the combined effect of thermal diffusion and migration towards the surface during MBE growth. This study points out that a low substrate temperature (≤540 °C) and a short time are required during MBE crystal growth to achieve confined δ doping.

CH4/H2 reactive ion etching for gate recessing of pseudomorphic modulation doped field effect transistors

Pseudomorphic AlGaAs/InGaAs modulation doped field effect transistors have been fabricated by using methane/hydrogen (CH4/H2) reactive ion etching for gate recessing. Source‐drain resistance and Hall measurements on as etched and annealed samples are presented. The electrical degradation introduced by the plasma can be recovered after annealing at 400 °C. A threshold voltage (Vth) standard deviation of 14 mV over a 5 cm (2 in.) wafer was obtained.

RF ESD protection strategies - the design and performance trade-off challenges

ESD protection strategies utilized in RF circuit applications in CMOS and BiCMOS technologies are investigated and the results are presented in this paper. The conventional approach using diodes with power clamp is compared with novel approaches such as plug-and-play passive elements and full or partial circuit-ESD co-design. The trade-offs are discussed from both RF and ESD point of views. Common problems as parasitic ESD current discharge paths and voltage overshoot are discussed and solutions are proposed

ESD circuit model based protection network optimisation for extended-voltage NMOS drivers

Abstract New snapback circuit models for drain extended MOS (DEMOS) and complementary DEMOS-SCR structures used for ESD protection in high-voltage tolerant applications have been developed. The models were experimentally validated in a standard 0.35 μm CMOS process which requires 20 V compatible structures. It is shown that the new ESD models provide accurate representation of the structure breakdown, turn-on behaviour into conductivity modulation mode and dV/dt triggering effect, both in static and ESD transient conditions. A major application of this model is for initial ESD optimisation of complex mixed voltage analog circuits.

Advanced modelling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies

The electro-static discharge (ESD) breakdown mechanism of 90 nm MOSFET n+/pwell devices is described in detail and modelled with a physics based equation set. The newly developed consistent parameter extraction approach allows to overcome the limitations of existing methodologies, which are not applicable for the 90 nm CMOS node device behaviour, and to calibrate precisely the snapback models. These models will help optimising the ESD robust I/O cells, which use 90 nm MOSFET devices as I/O drivers and ESD structures.

Voltage overshoot study in 20V DeMOS-SCR devices

Based upon measurements of the HBM waveforms of DeMOS-SCR devices, the voltage overshoot during turn-on is studied as a function of device architecture and gate sub-circuit. It has been demonstrated that, in general, the overshoot voltage does not correlate to the TLP triggering voltage, but can be controlled in a wide range both at the device level and at the gate sub-circuit level by modifying blocking junction breakdown voltage, gate coupling and displacement current density in the internal parasitic BJT.

Scaling behavior of delta‐doped AlGaAs/InGaAs high electron mobility transistors with gatelengths down to 60 nm and source‐drain gaps down to 230 nm

Pseudomorphic delta‐doped AlGaAs/InGaAs/GaAs high electron mobility transistors with gatelengths ranging from 60 to 250 nm have been fabricated in submicron source‐drain gaps using high‐resolution electron beam lithography. As a consequence of short channel effects, the maximum transconductance gm is not improved by decreasing the gatelength from 250 nm (950 mS/mm) to 60 nm (800 mS/mm). When comparing high‐frequency (HF) and direct‐current values of the peak transconductances for devices with gatelengths shorter than 100 nm, the HF performance is remarkably higher. The difference can be explained by the fact that short channel effects are less important at high frequencies. Due to the decrease of the gate capacitance, the transition frequency fT increases as the gatelength is reduced.

Submicron Pseudomorphic Hemt’S Using Non-Alloyed Ohmic Contacts with Contrast Enhancement.

We report for the first time the realization of submicron pseudomorphic Al. 15 , Ga .85 As-In .20 Ga .80 As HEMT’s with non-alloyed Pd/Ge ohmic coi tacts. Best results of contact resistance were obtained at a sintering temperature of 340°C with values as low as 0.057 Ωmm. Enhanced contrast, needed for accurate alignment of the gate by electron-beam lithography, was obtained by using Pd/Ge/Ti/Pd and Pd/Ge/Ti/Pt metal sequences. These contacts exhibited even lower contact resistances than the standard Pd/Ge contacts. Although Pd/Ge/Ti/Pd exhibits good morphology, reaction is witnessed at the edges, reducing the accuracy of alignment. Processed enhancement mode devices exhibit maximum transconductances in excess of 520 mS/mm and currents of 300 mA/mm for 0.3 micron gatelength. This study shows that the contact resistance is no longer a restriction for obtaining very high transconductances in high performance devices.