M.I. Natarajan

Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage

The physical mechanisms that influence the triggering and holding voltage in a DMOS transistor in CMOS smart power technology are investigated. We demonstrate that a high and a low holding voltage device can be designed by changing the lateral bipolar base distance and that also the trigger voltage can be easily tuned. The layout variation that controls the holding voltage also leads to a different snapback mechanism and a different current flow through the device. Excellent ESD capabilities of 16-20 mA//spl mu/m width have been achieved.

Calibrated wafer-level HBM measurements for quasi-static and transient device analysis

An improved calibration methodology for simultaneous capturing of voltage and current during an HBM pulse is presented. The capability of this new methodology for ESD protection device characterization and development is demonstrated using the quasi-static and transient response analysis of silicon-controlled rectifier devices.

A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS

A 5.5 GHz fully integrated low-power ESD-protected low-noise amplifier (LNA), designed and verified in a 90 nm RF CMOS technology, is presented for the first time. This 9.7 mW LNA features a 13.3 dB power gain with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB.

Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drain

Ultra deep submicron CMOS is a promising technology for wireless applications. In order to obtain an optimal RF performance, many trade-offs can be made during the development of a CMOS technology that is traditionally driven by digital requirements. Using logic devices from a 90 nm digital CMOS technology node, RF models are generated that allow feedback from RF designs and optimisation of the technology for RF applications. As a case study, the elevated source drain (/sup E/S/D) architecture is optimised for RF performance. The influence of this process optimisation on an extrinsic reliability threat is investigated using Electro-Static Discharge (ESD) withstanding capability.

Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors

Above-IC inductors enable low-power RF circuit design, and in addition efficiently protect the RF pins against electrostatic discharge (ESD) stress. This is demonstrated using above-IC inductors in the design of a fully integrated 5 GHz ESD-protected LNA and VCO in 90 nm CMOS. The LNA without ESD protection shows 1.4 dB NF, with 18 dB gain, drawing 4 mA from a 1.2 V supply. The ESD protected LNA has a 2.2 dB NF and 17.6 dB gain while sustaining human body model (HBM) ESD stress of above 8 kV. The 5.4 GHz VCO has a current consumption of 150 muA with a 1.2 V supply, and a 10 % tuning range with a worst case phase noise of -111 dBc/Hz at 1 MHz offset

ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS — Implementation concepts, constraints and solutions

Design and implementation of ESD protection for a 5.5 GHz Low Noise Amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as ldquoplug-and-playrdquo, is used as ESD protection for the RF pins. The consequences of design and process, as well as the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail and additional improvements are suggested.

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.

RF ESD protection strategies - the design and performance trade-off challenges

ESD protection strategies utilized in RF circuit applications in CMOS and BiCMOS technologies are investigated and the results are presented in this paper. The conventional approach using diodes with power clamp is compared with novel approaches such as plug-and-play passive elements and full or partial circuit-ESD co-design. The trade-offs are discussed from both RF and ESD point of views. Common problems as parasitic ESD current discharge paths and voltage overshoot are discussed and solutions are proposed

Snapback circuit model for cascoded NMOS ESD over-voltage protection structures

This paper presents an equivalent circuit snapback model for the ESD domain operation of merged cascoded NMOS devices. The model reflects the specific breakdown operation of the structure at different gate bias conditions. An example for optimisation of the ESD behaviour of an output driver, utilising this protection device, is presented.

Multilevel Transmission Line Pulse (MTLP) tester

A novel TLP testing approach, multilevel TLP (MTLP), is described, which can yield accurate and comprehensive snapback IV measurements unlike in the conventional TLP testing methodology with different system impedances. The experimental validity of the MTLP methodology and setup are demonstrated with measurement results from different snapback devices.