Vesselin Vassilev

Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drain

Ultra deep submicron CMOS is a promising technology for wireless applications. In order to obtain an optimal RF performance, many trade-offs can be made during the development of a CMOS technology that is traditionally driven by digital requirements. Using logic devices from a 90 nm digital CMOS technology node, RF models are generated that allow feedback from RF designs and optimisation of the technology for RF applications. As a case study, the elevated source drain (/sup E/S/D) architecture is optimised for RF performance. The influence of this process optimisation on an extrinsic reliability threat is investigated using Electro-Static Discharge (ESD) withstanding capability.

ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS — Implementation concepts, constraints and solutions

Design and implementation of ESD protection for a 5.5 GHz Low Noise Amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as ldquoplug-and-playrdquo, is used as ESD protection for the RF pins. The consequences of design and process, as well as the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail and additional improvements are suggested.

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.

RF ESD protection strategies - the design and performance trade-off challenges

ESD protection strategies utilized in RF circuit applications in CMOS and BiCMOS technologies are investigated and the results are presented in this paper. The conventional approach using diodes with power clamp is compared with novel approaches such as plug-and-play passive elements and full or partial circuit-ESD co-design. The trade-offs are discussed from both RF and ESD point of views. Common problems as parasitic ESD current discharge paths and voltage overshoot are discussed and solutions are proposed

Thin L-shaped spacers for CMOS devices

This work presents the use of ultimately thin (15 nm) L-shaped spacers to open the process window for deposition-related steps. Whereas conventional spacers prevent the correct active area silicidation between two closely located transistors, these thin L-shaped spacers allow the formation of a low resistive active interconnect between transistors as close as 40 nm apart. With respect to conventional spacers, thin L-shaped spacers show equally good silicide bridging immunity, device characteristics and electrostatic discharge performance.

Snapback circuit model for cascoded NMOS ESD over-voltage protection structures

This paper presents an equivalent circuit snapback model for the ESD domain operation of merged cascoded NMOS devices. The model reflects the specific breakdown operation of the structure at different gate bias conditions. An example for optimisation of the ESD behaviour of an output driver, utilising this protection device, is presented.

Multilevel Transmission Line Pulse (MTLP) tester

A novel TLP testing approach, multilevel TLP (MTLP), is described, which can yield accurate and comprehensive snapback IV measurements unlike in the conventional TLP testing methodology with different system impedances. The experimental validity of the MTLP methodology and setup are demonstrated with measurement results from different snapback devices.

ESD circuit model based protection network optimisation for extended-voltage NMOS drivers

Abstract New snapback circuit models for drain extended MOS (DEMOS) and complementary DEMOS-SCR structures used for ESD protection in high-voltage tolerant applications have been developed. The models were experimentally validated in a standard 0.35 μm CMOS process which requires 20 V compatible structures. It is shown that the new ESD models provide accurate representation of the structure breakdown, turn-on behaviour into conductivity modulation mode and dV/dt triggering effect, both in static and ESD transient conditions. A major application of this model is for initial ESD optimisation of complex mixed voltage analog circuits.

Dynamic substrate resistance snapback triggering of ESD protection devices

This paper describes a novel approach to design self-triggered ESD protection structures. It consists in adding a reverse biased p-n junction in the path of the current, flowing into the base of the ESD activated parasitic BIT device. As a result, the base resistance of the parasitic BIT is increased, which in turn leads to faster and more uniform snapback triggering. The ESD threshold levels for the investigated structures designed in the new approach are found to increase. MEDICI simulations, in combination with TLP and EMMI characterization are performed to study the structure operation.

Advanced modelling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies

The electro-static discharge (ESD) breakdown mechanism of 90 nm MOSFET n+/pwell devices is described in detail and modelled with a physics based equation set. The newly developed consistent parameter extraction approach allows to overcome the limitations of existing methodologies, which are not applicable for the 90 nm CMOS node device behaviour, and to calibrate precisely the snapback models. These models will help optimising the ESD robust I/O cells, which use 90 nm MOSFET devices as I/O drivers and ESD structures.